參數(shù)資料
型號(hào)： PSD813F2V-70
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述： Flash在系統(tǒng)可編程（ISP）的周邊8位MCU，5V的
文件頁(yè)數(shù)： 17/110頁(yè)
文件大?。?/td> 1685K
代理商： PSD813F2V-70
17/110
PSD813F1
PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table
5
shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table
6
provides brief descriptions of the registers
in CSIOP space. The following section gives a
more detailed description.
Table 5. I/O Port Latched Address Output Assignments
Note: 1. See the section entitled
I/O PORTS, page 52
, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
Table 6. Register Address Offset
Note: 1. Other registers that are not part of the I/O ports.
MCU
(1)
Port A
(2)
Port B
(2)
Port A (3:0)
N/A
N/A
Address a3-a0
N/A
Port A (7:4)
Address a7-a4
N/A
Address a7-a4
N/A
Port B (3:0)
Address a11-a8
Address a11-a8
Address a3-a0
Address a3-a0
Port B (7:4)
8051XA (8-bit)
80C251 (page mode)
All other 8-bit multiplexed
8-bit non-multiplexed bus
N/A
Address a15-a12
Address a7-a4
Address a7-a4
Register Name
Port
A
00
02
Port
B
01
03
Port
C
10
Port
D
11
Other
(1)
Description
Data In
Control
Reads Port pin as input, MCU I/O input mode
Selects mode between MCU I/O or Address Out
Stores data for output to Port pins, MCU I/O output
mode
Configures Port pin as input or output
Configures Port pins as either CMOS or Open Drain
on some pins, while selecting high slew rate on other
pins.
Reads Input Macrocells
Reads the status of the output enable to the I/O Port
driver
READ
–
reads output of macrocells AB
WRITE
–
loads macrocell flip-flops
READ
–
reads output of macrocells BC
WRITE
–
loads macrocell flip-flops
Data Out
04
05
12
13
Direction
06
07
14
15
Drive Select
08
09
16
17
Input Macrocell
0A
0B
18
Enable Out
0C
0D
1A
1B
Output Macrocells
AB
Output Macrocells
BC
Mask Macrocells
AB
Mask Macrocells
BC
Primary Flash
Protection
Secondary Flash
memory
Protection
JTAG Enable
PMMR0
PMMR2
Page
20
20
21
21
22
22
Blocks writing to the Output Macrocells AB
23
23
Blocks writing to the Output Macrocells BC
C0
Read only
–
Flash Sector Protection
C2
Read only
–
PSD Security and EEPROM Sector
Protection
C7
B0
B4
E0
Enables JTAG Port
Power Management Register 0
Power Management Register 2
Page Register
Places PSD memory areas in Program and/or Data
space on an individual basis.
VM
E2
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