- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378074 > PSD813F2V-70 (意法半導體) Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V PDF資料下載
參數(shù)資料
| 型號： | PSD813F2V-70 |
| 廠商： | 意法半導體 |
| 英文描述： | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| 中文描述： | Flash在系統(tǒng)可編程（ISP）的周邊8位MCU，5V的 |
| 文件頁數(shù)： | 21/110頁 |
| 文件大?。?/td> | 1685K |
| 代理商： | PSD813F2V-70 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁
21/110
PSD813F1
INSTRUCTIONS
An instruction is defined as a sequence of specific
operations. Each received byte is sequentially de-
coded by the PSD and not executed as a standard
write operation. The instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out value. Some instructions
are structured to include READ operations after
the initial WRITE operations.
The sequencing of any instruction must be fol-
lowed exactly. Any invalid combination of instruc-
tion bytes or time-out between two consecutive
bytes while addressing Flash memory will reset
the device logic into READ mode (Flash memory
reads like a ROM device). An invalid combination
or time-out while addressing the EEPROM block
will cause the offending byte to be interpreted as a
single operation.
The PSD supports these instructions (see
Table
8., page 20
):
Flash memory:
Erase memory by chip or sector
Suspend or resume sector erase
Program a Byte
Reset to READ mode
Read Flash Identifier value
Read Sector Protection Status
EEPROM:
Write data to OTP Row
Read data from OTP Row
Power down memory
Enable Software Data Protect (SDP)
Disable SDP
Return from read OTP Row read mode or
power down mode.
I
I
I
I
I
I
I
I
I
I
I
I
These
8., page 20
. For efficient decoding of the instruc-
tions, the first two bytes of an instruction are the
coded cycles and are followed by a command byte
or confirmation byte. The coded cycles consist of
writing the data AAh to address X555h during the
first cycle and data 55h to address XAAAh during
the second cycle. Address lines A15-A12 are don
’
t
cares during the instruction WRITE cycles. How-
ever, the appropriate sector select signal (FSi or
EESi) must be selected.
Power-down Instruction and Power-up Mode
EEPROM Power Down Instruction.
The
PROM can enter power down mode with the help
of the EEPROM power down instruction (see
Ta-
ble 8., page 20
). Once the EEPROM power down
instruction is decoded, the EEPROM memory can-
not be accessed unless a Return instruction (also
in
Table 8., page 20
) is decoded. Alternately, this
power down mode will automatically occur when
the APD circuit is triggered (see section entitled
Automatic Power-down (APD) Unit and Power-
down Mode, page 65
). Therefore, this instruction
is not required if the APD circuit is used.
Power-up Mode.
The PSD internal logic is reset
upon power-up to the READ mode. Any write op-
eration to the EEPROM is inhibited during the first
5ms following power-up. The FSi and EESi select
signals, along with the write strobe signal, must be
in the false state during power-up for maximum se-
curity of the data contents and to remove the pos-
sibility of a byte being written on the first edge of a
write strobe signal. Any write cycle initiation is
locked when V
CC
is below V
LKO
.
instructions
are
detailed
in
Table
EE-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD813F2V-90 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F3 | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F3V-15 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F3V-20 | Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F3V-70 | Resonant-Mode Power Supply Controllers 16-SOIC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD813F2V-70J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F2V-70J1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 3.3 V |
| PSD813F2V-70JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F2V-70JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F2V-70JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發(fā)布緊急采購，3分鐘左右您將得到回復。