參數(shù)資料
型號(hào): PSD813F5V-90
廠商: 意法半導(dǎo)體
英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述: Flash在系統(tǒng)可編程(ISP)的周邊8位MCU,5V的
文件頁(yè)數(shù): 25/110頁(yè)
文件大?。?/td> 1685K
代理商: PSD813F5V-90
25/110
PSD813F1
Writing the OTP Row
Writing to the OTP row (64 bytes) can only be
done once per byte, and is enabled by an instruc-
tion. This instruction is composed of three specific
WRITE operations of data bytes at three specific
memory locations followed by the data to be
stored in the OTP row (refer to
Table 8., page 20
).
During the WRITE operations, address bit A6 must
be zero, while address bits A5-A0 define the OTP
Row byte to be written while any EEPROM Sector
Select signal (EESi) is active. Writing the OTP
Row is allowed only when SDP mode is not en-
abled.
Figure 7. EEPROM SDP Enable Flowcharts
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE A0h to
Address 555h
SDP is set
Page Write
Instruction
SDP ENABLE ALGORITHM
WRITE AAh to
Address 555h
WRITE 55h to
Address AAAh
WRITE A0h to
Address 555h
Page Write
Instruction
SDP
Set
SDP
not Set
WRITE
is enabled
WRITE Data to
be Written in
any Address
Write
in Memory
Write Data
+
SDP Set
after tWC
(Write Cycle Time)
ai09219
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