參數(shù)資料
型號: PSD813F5V-90
廠商: 意法半導體
英文描述: Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
中文描述: Flash在系統(tǒng)可編程(ISP)的周邊8位MCU,5V的
文件頁數(shù): 97/110頁
文件大?。?/td> 1685K
代理商: PSD813F5V-90
97/110
PSD813F1
Figure 51. Reset (RESET) Timing
Table 67. Reset (RESET) Timing (5V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 68. Reset (RESET) Timing (3V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. t
NLNH-PO
is 10ms for devices manufactured before the rev.A.
Table 69. V
STBYON
Timing (5V devices)
Symbol
Table 70. V
STBYON
Timing (3V devices)
Symbol
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
1
150
ns
t
NLNH
PO
Power On Reset Active Low Time
1
ms
t
OPR
RESET High to Operational Device
120
ns
Symbol
Parameter
Conditions
Min
Max
Unit
t
NLNH
RESET Active Low Time
1
300
ns
t
NLNH
PO
Power On Reset Active Low Time
2
1
ms
t
OPR
RESET High to Operational Device
300
ns
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1
)
20
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1
)
20
μs
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
V
STBY
Detection to V
STBYON
Output High
(Note
1
)
2.0
μs
t
BXBL
V
STBY
Off Detection to V
STBYON
Output
Low
(Note
1
)
2.0
μs
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
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