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參數(shù)資料
| 型號： | PSD833F2-15M |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 35/122頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PSD833F2-15M |
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PSD8XXF2 PSD8XXF3
PSD8XXF4 PSD8XXF5
Flash In-System-Programmable Microcontroller Peripherals
Table of Contents
1.0
Introduction ...........................................................................................................................................................1
2.0
Key Features ........................................................................................................................................................2
PSD8XXF Block Diagram...............................................................................................................................4
3.0
General Information ..............................................................................................................................................5
4.0
PSD8XXF Family ..................................................................................................................................................5
5.0
PSD8XXF Architectural Overview ........................................................................................................................6
5.1 Memory ...................................................................................................................................................6
5.2 Page Register .........................................................................................................................................6
5.3 PLDs .......................................................................................................................................................6
5.4 I/O Ports..................................................................................................................................................7
5.5 Microcontroller Bus Interface ..................................................................................................................7
5.6 JTAG Port ...............................................................................................................................................7
5.7 In-System Programming .........................................................................................................................8
5.8 Power Management................................................................................................................................8
6.0
Development System............................................................................................................................................9
7.0
PSD8XXF Pin Descriptions ................................................................................................................................10
8.0
PSD8XXF Register Description and Address Offset ..........................................................................................14
9.0
PSD8XXF Functional Blocks ..............................................................................................................................15
9.1 Memory Blocks .....................................................................................................................................15
9.1.1 Main Flash and Flash Boot Memory Description........................................................................15
9.1.2 SRAM .........................................................................................................................................27
9.1.3 Memory Select Signals...............................................................................................................27
9.1.4 Page Register.............................................................................................................................30
9.2 PLDs .....................................................................................................................................................31
9.2.1 Decode PLD (DPLD) ..................................................................................................................33
9.2.2 Complex PLD (CPLD) ................................................................................................................33
9.3 Microcontroller Bus Interface ................................................................................................................42
9.3.1 PSD8XXF Interface to a Multiplexed 8-Bit Bus ..........................................................................42
9.3.2 PSD8XXF Interface to a Non-Multiplexed 8-bit Bus...................................................................42
9.3.3 Data Byte Enable Reference......................................................................................................45
9.3.4 Microcontroller Interface Examples ............................................................................................45
9.4 I/O Ports................................................................................................................................................50
9.4.1 General Port Architecture...........................................................................................................50
9.4.2 Port Operating Modes ................................................................................................................52
9.4.3 Port Configuration Registers (PCRs) .........................................................................................55
9.4.4 Port Data Registers ....................................................................................................................58
9.4.5 Ports A and B – Functionality and Structure ............................................................................59
9.4.6 Port C – Functionality and Structure ........................................................................................61
9.4.7 Port D – Functionality and Structure ........................................................................................61
9.5 Power Management..............................................................................................................................65
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode .....................................................65
9.5.2 Other Power Saving Options......................................................................................................69
9.5.3 Reset and Power On Requirement ............................................................................................70
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
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