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| 型號(hào)： | PSD833F2-15M |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁(yè)數(shù)： | 89/122頁(yè) |
| 文件大?。?/td> | 489K |
| 代理商： | PSD833F2-15M |
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Preliminary Information
PSD8XXF Family
65
9.5 Power Management
The PSD8XXF offers configurable power saving options. These options may be used
individually or in combinations, as follows:
All memory types in a PSD (Flash, Flash Boot Block, and SRAM) are built with
Zero-Power technology. In addition to using special silicon design methodology,
Zero-Power technology puts the memories into standby mode when address/data
inputs are not changing (zero DC current). As soon as a transition occurs on an input,
the affected memory “wakes up”, changes and latches its outputs, then goes back to
standby. The designer does not have to do anything special to achieve memory
standby mode when no inputs are changing—it happens automatically.
The PLD sections can also achieve standby mode when its inputs are not changing,
see PMMR registers below.
Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The APD will block MCU address/data signals
from reaching the memories and PLDs. This feature is available on all PSD8XXF
devices. The APD unit is described in more detail in section 9.5.1.
Built in logic will monitor the address strobe of the MCU for activity. If there is no
activity for a certain time period (MCU is asleep), the APD logic initiates Power Down
Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked
from reaching PSD memories and PLDs, and the memories are deselected internally.
This allows the memories and PLDs to remain in standby mode even if the
address/data lines are changing state externally (noise, other devices on the MCU
bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states
keeps the PLD out of standby mode, but not the memories.
The PSD Chip Select Input (CSI) on all families can be used to disable the internal
memories, placing them in standby mode even if inputs are changing. This feature
does not block any internal signals or disable the PLDs. This is a good alternative to
using the APD logic, especially if your MCU has a chip select output. There is a slight
penalty in memory access time when the CSI signal makes its initial transition from
deselected to selected.
The PMMR registers can be written by the MCU at run-time to manage power. All PSD
devices support “blocking bits” in these registers that are set to block designated
signals from reaching both PLDs. Current consumption of the PLDs is directly related
to the composite frequency of the changes on their inputs (see Figures 31 and 31a).
Significant power savings can be achieved by blocking signals that are not used in
DPLD or CPLD logic equations.
The PSD8XXF devices have a Turbo Bit in the PMMR0 register. This bit can be set to
disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is
disabled, the PLDs can achieve standby current when no PLD inputs are changing
(zero DC current). Even when inputs do change, significant power can be saved at
lower frequencies (AC current), compared to when Turbo Mode is enabled. Conversely,
when the Turbo Mode is enabled, there is a significant DC current component and the
AC component is higher.
9.5.1 Automatic Power Down (APD) Unit and Power Down Mode
The APD Unit, shown in Figure 28, puts the PSD into Power Down Mode by monitoring
the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity
on the address strobe stops, a four bit counter starts counting. If the address strobe
remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN)
signal becomes active, and the PSD will enter into Power Down Mode, discussed next.
The
PSD8XXF
Functional
Blocks
(cont.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
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