參數(shù)資料
型號: PSD913370MT
廠商: 意法半導(dǎo)體
英文描述: Quad CMOS to PECL Translator; Package: 20 LEAD PLLC; No of Pins: 20; Container: Rail; Qty per Container: 46
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù): 23/110頁
文件大小: 1737K
代理商: PSD913370MT
23/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Reading the Erase/Program Status Bits
The PSD provides several status bits to be used
by the MCU to confirm the completion of an Erase
or Program cycle of Flash memory. These status
bits minimize the time that the MCU spends per-
forming these tasks and are defined in Table
10
.
The status bits can be read as many times as
needed.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entitled
PROGRAMMING FLASH MEMORY, page 25
for
details.
Table 10. Status Bit
Note: 1. X = Not guaranteed value, can be read either '1' or ’0.’
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FS0-FS7 and CSBOOT0-CSBOOT3 are active High.
Functional Block
FS0-FS7/CSBOOT0-
CSBOOT3
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Flash Memory
V
IH
Data
Polling
Toggle
Flag
Error
Flag
X
Erase
Time-
out
X
X
X
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