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    參數(shù)資料
    型號(hào): PSD935G1-B-20U
    廠(chǎng)商: 意法半導(dǎo)體
    英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)
    文件頁(yè)數(shù): 32/91頁(yè)
    文件大小: 488K
    代理商: PSD935G1-B-20U
    PSD935G2
    PSD9XX Family
    31
    The
    PSD935G2
    Functional
    Blocks
    (cont.)
    9.1.5 Memory ID Registers
    The 8-bit read only memory status registers are included in the CSIOP space. The user
    can determine the memory configuration of the PSD device by reading the Memory ID0
    and Memory ID1 registers. The content of the registers are defined as follow:
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    S_size 3
    S_size 2
    S_size 1
    S_size 0
    F_size 3
    F_size 2
    F_size 1
    F_size 0
    Memory_ID0 Register
    Main Flash Size
    (Bit)
    none
    256K
    512K
    1M
    2M
    4M
    8M
    F_size3
    0
    0
    0
    0
    0
    0
    0
    F_size2
    0
    0
    0
    0
    1
    1
    1
    F_size1
    0
    0
    1
    1
    0
    0
    1
    F_size0
    0
    1
    0
    1
    0
    1
    0
    Bit Definition
    SRAM Size
    (Bit)
    none
    16K
    32K
    64K
    S_size3
    0
    0
    0
    0
    S_size2
    0
    0
    0
    0
    S_size1
    0
    0
    1
    1
    S_size0
    0
    1
    0
    1
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    *
    *
    B_type 1
    B_type 0
    B_size 3
    B_size 2
    B_size 1
    B_size 0
    Memory_ID1 Register
    *
    Not used bit should be set to zero.
    Boot Block Size
    (Bit)
    none
    128K
    256K
    512K
    B_size3
    0
    0
    0
    0
    B_size2
    0
    0
    0
    0
    B_size1
    0
    0
    1
    1
    B_size0
    0
    1
    0
    1
    Bit Definition
    B_type1
    0
    0
    B_type0
    0
    1
    Boot Block Type
    Flash
    EEPROM
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