參數(shù)資料
型號(hào): PSD953212JIT
廠商: 意法半導(dǎo)體
英文描述: High Speed CMOS Logic Quad 2-Input NAND Gates 14-SOIC -55 to 125
中文描述: Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁(yè)數(shù): 68/110頁(yè)
文件大?。?/td> 1737K
代理商: PSD953212JIT
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
68/110
Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to '0' on Power-On Reset or Warm Reset.
Port Configuration
Power-On Reset
Warm Reset
Power-down Mode
MCU I/O
Input mode
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Tri-stated
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to '0'
Unchanged
Unchanged
Macrocells flip-flop status
Cleared to '0' by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register
1
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to '0'
Cleared to '0'
Unchanged
相關(guān)PDF資料
PDF描述
PSD953212JT High Speed CMOS Logic Quad 2-Input NAND Gates 14-SOIC -55 to 125
PSD953212MT Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD9332V15JT High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125
PSD9332V15MT High Speed CMOS Logic Quad 2-Input NAND Gates with Open Drain 14-SOIC -55 to 125
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