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Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
PT0106(09/02)
Ver:0
1
Features
Supports AT&T TR62411 Stratum 3, 4 and
Stratum 4 Enhanced for DS1 interfaces and for
ETSI ETS 300 011, TBR 4, TBR 12, and TBR
13 for E1 interfaces
Supports ITU-T G.812 Type IV clocks for
1.544kbit/s interfaces and 2.048kbit/s interface
Provides C1.5, C3, C2, C4, C8, C6, C16 and C19
output clock signals
Provides five kinds of 8kHz ST-BUS framing
signals
Two independent reference inputs
Input reference frequency 1.544MHz, 2.048MHz
or 8kHz selectable
Provides bit error free reference switching and
meets phase slope and MTIE requirements
Normal, Holdover or Free-Run operating modes
available
Holdover accuracy: ±0.2ppm
Automatic reference input impairment monitor
Power supply: 5V (4410) and 3.3V(4410L)
Applications
Synchronization and timing control for multitrunk
T1 and E1 systems, STS-3/OC3 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
Introduction
PT7A4410/4410L employs a digital phase-locked
loop (DPLL) to provide timing and synchronizing
signals for multitrunk T1 and E1 primary rate
transmission links, and for STS-3/OC3 links. The ST-
BUS clock and framing signals are phase-locked to
input reference signals of either 2.048 MHz,
1.544MHz or 8 kHz.
The PT7A4410/4410L meets the requirements for
AT&T TR62411 Stratum 3, 4 and Stratum 4 En-
hanced, and ETSI ETS 300 011 in jitter tolerance,
jitter transfer, intrinsic jitter, frequency accuracy, hold-
over accuracy, capture range, phase slope and MTIE,
etc.
The PT7A4410/4410L operates in Manual or Auto-
matic Mode, and in each of the modes, three operat-
ing states are available: Normal, Holdover and Free-
Run.
Ordering Information
r
b
r
m
u
u
N
t
P
e
g
a
k
c
a
P
J
0
1
4
4
A
7
T
P
C
C
L
P
n
-
4
J
L
0
1
4
4
A
7
T
P
C
C
L
P
n
-
4