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參數(shù)資料
| 型號： | PT7A4410J |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | T1/E1/OC3 System Synchronizer |
| 中文描述： | T1/E1/OC3系統(tǒng)同步 |
| 文件頁數(shù)： | 14/34頁 |
| 文件大?。?/td> | 294K |
| 代理商： | PT7A4410J |
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Data Sheet
PT7A4410/4410L
T1/E1/OC3 System Synchronizer
PT0106(09/02)
Ver:0
14
Applications Information
Master Clock
The PT7A4410/4410L uses either an external clock source or
an external crystal as the master timing source.
In Free-Run State, the frequency tolerance of the PT7A4410/
4410L output clocks are equal to the frequency tolerance of
the timing source. In an application, if an accurate Free-Run
State is not required, the tolerance of the master timing source
may be 100ppm. If required, the tolerance must be no greater
than 32ppm.
The capture range of PT7A4410/4410L will also be consid-
ered when deciding the accuracy of the master timing source.
The sum of the accuracy of the master timing source and the
capture range of the PT7A4410/4410L will always equal
230ppm. For example, if the master timing source is 100ppm,
the capture range will be 130ppm.
Clock Oscillator
If using an external clock source, its output pin should be
connected directly (not AC coupled) to the OSCi pin of the
PT7A4410/4410L and the OSCo pin of PT7A4410/4410L can
be left open as shown in Figure 9 or connected as an output
pin.
Figure 9. Clock Oscillator Connection
Crystal Oscillator
If a crystal oscillator is selected as the master timing source, it
should be connected to the PT7A4410/4410L as shown in
Figure 10.
Figure 10. Crystal Oscillator Connection
The crystal specification is as follows:
- Frequency:
- Tolerance:
- Oscillation Mode:
- Resonance Mode:
- Load Capacitance:
- Maximum Series Resistance:
-
Α
pproximate Drive Level:
20MHz
as required
Fundamental
Parallel
32pF
35
1mW
Guard Time Adjustment Circuit
AT&T TR62411 recommends that excessive switching of the
timing reference should be minimized. Switching between ref-
erences should be performed only when the primary signal is
degraded.
The Holdover State is used to minimize reference source
switching (from PRI to SEC). When the PRI signal is degraded,
the PT7A4410/4410L enters Holdover State for a predeter-
mined maximum time (i.e., guard time). If the PRI signal re-
turns to normal before the expiration of the guard time (level
at GTi pin is low), the PT7A4410/4410L will return to Normal
State with PRI input reference. If the PRI signal is still de-
graded after expiration of the guard time (level at GTi be-
comes high), the reference switching (from PRI to SEC) will
occur.
When selecting the clock oscillator, following specifications
should be considered. They are
- absolute frequency
- frequency change over temperature
- output rise and fall time
- output level
- duty cycle
Refer to AC Electrical Characteristics.
+5V
20MHz OUT
GND
PT7A4410/4410L
OSCi
OSCo
+5V
No Connection
0.1
μ
F
PT7A4410/4410L
56pF
1M
20MHz
39pF
3-50pF
OSCi
OSCo
100
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