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參數(shù)資料
| 型號： | PT7A8980 |
| 英文描述： | 100V Quad N-Channel HEXFET Power MOSFET in a Power MLP package |
| 中文描述： | 256端口無阻塞時隙開關(guān)？ |技術(shù)資料？（PDF格式） |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 220K |
| 代理商： | PT7A8980 |
7
PT0011(09/02)
Ver:3
Data Sheet
PT7A8980/8980L Digital Switch
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Bit 6, when 1, sets all the 256 output channels of the chip into
Message Mode. In this mode, the Contents of all Connection
Memory Low are output on the ST-BUS output data streams
every frame unless the ODE pin is low. The chip behaves as if
the bits 2 and 0 of every Connection Memory High location
were 1.
Bits 4~3 are the Memory Select bits that determine the ac-
cessed location is in the Connection Memory High, Low or
Data Memory.
The Data Stream Select bits, Bits 0~2, specify which memory
location of the eight input and output data streams is addressed.
Figure 3. Control register Bits
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Table 4. Control Register Bits
ST-BUS Timing Reference
All ST-BUS timing is referenced to the C4i and F0i inputs.
These two clock signals must be synchronized to each other,
and compliant with the timing requirements specified in Fig-
ure 9. The C4i is a 4.096 MHz clock, and the F0i at 8 kHz is
the frame synchronization signal of data stream.
Control Register
The data in the Control Register consists of Mode Control
bits, Memory Select bits and Data Stream Address bits (see
Figure 3 and Table 4). The Mode Control bits consist of bits
6~7. Bit 7 of the Control Register can put the chip in the Split
Read and Write mode where reads are from the Data Memory
and writes are to the Connection Memory Low.
7
6
5
4
3
2
1
0
Mode Control Bits Unused Bit Memory Select Bits Data Stream Address Bits
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