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Interrupt related bits
INTCN
Interrupt Output pin select bit.
This bit controls the relationship between the two alarms and the interrupt output pins.
INTCN
Data
PT0205(02/07)
Ver: 1
8
Data Sheet
PT7C4337
Real-time Clock Module (I
2
C Bus)
Description
1
A match between the timekeeping registers and the alarm 1 registers activates the INTA pin (if the
alarm 1 is enabled) and a match between the timekeeping registers and the alarm 2 registers activates
the SQW/INTB pin (if the alarm 2 is enabled).
Read /
Write
0
A match between the timekeeping registers and either alarm 1 or alarm 2 registers activates
the INTA pin (if the alarms are enabled). In this configuration, a square wave is output on
the SQW/INTB pin.
Default
Alarm 1 Interrupt Enable.
A1IE
A1IE
Data
Description
0
The A1F bit does not initiate the INTA signal.
Default
Read /
Write
1
Permits the alarm 1 flag (A1F) bit in the status register to assert INTA.
Alarm 1 Flag.
A1F
A1F
Data
Description
Read / Write
0
The time do not match the alarm 1 registers.
Default
Read
1
Indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes
low. A1F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
Alarm 2 Interrupt Enable.
A2IE
A2IE
Data
Description
0
The A2F bit does not initiate an interrupt signal.
Default
Read /
Write
1
Permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert
SQW/INTB (when INTCN = 1).
Alarm 2 Flag.
A1F
A2F
Data
Description
Read /
Write
0
The time do not match the alarm 2 registers.
Default
Read
1
Indicates that the time matched the alarm 1 registers. This flag can be used to generate an interrupt on
either INTA or SQW/INTB depending on the status of the INTCN bit. If the INTCN = 0 and A2F = 1
(and A2IE = 1), the INTA pin goes low. If the INTCN = 1 and A2F = 1 (and A2IE = 1), the
SQW/INTB pin goes low. A2F is cleared when written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.