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參數(shù)資料
| 型號： | PT8146L |
| 廠商： | Princeton Technology Corporation |
| 英文描述： | 8-Bit 12-Ch I/O DAC |
| 中文描述： | 8位12通道的I / O援 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 367K |
| 代理商： | PT8146L |
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Tel: 886-2-66296288
URL: http://www.princeton.com.tw
Fax: 886-2-29174598
PT8146 V1.1
- 27 -
February, 2006
8-Bit 12-Ch I/O DAC
PT8146
Symbol
A
A1
A2
*b
b1
c
c1
D
*E
E1
e
L
L1
N
R1
θ
Min.
-
0.05
1.65
0.22
0.22
0.09
0.09
7.90
7.60
5.00
Nom.
-
-
1.75
-
0.30
-
0.15
8.20
7.80
5.30
0.65 BASIC
0.75
1.25 REF
24
-
4
Max
2.0
-
1.85
0.32
0.33
0.25
0.21
8.50
8.00
5.60
0.55
0.95
0.09
0
-
8
Notes:
1.
2.
3.
All dimensions are in millimeters.
Dimension and tolerancing per ANSI Y14.5M-1982.
D and E1 dimension do not include mold flash or protrusions, but do include mold mismatch and
are measured at datum plane H, mold parting line. Mold flash or protrusion shall not exceed
0.20mm per side.
Dimension b does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13mm total in excess of b dimension at maximum material condition. Dambar intrusion shall
not reduce dimension b by more than 0.07mm at least material condition.
To be determined at the seating plane – datum “C”.
“N” is the number of terminal positions.
A visual index feature must be located within the crosshatched area.
These dimensions apply to the flat section to the lead between 0.10 and 0.25mm from the lead
tip.
Refer to JEDEC MO-150 variations AG
Dimensions marked with “
*
” are not complying with JEDEC product outlines.
JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
4.
5.
6.
7.
8.
9.
10.
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