PT0141(06/03)

Ver:0

4

Preliminary Data Sheet

PT8R2401MD 2.4GHz RF Module

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I/O Description

RF interface

The radio interface establishes the connection of antenna-to-LNA in receiving mode and antenna-to-power amplifier in

transmitting mode. An antenna filter is located between the antenna and SPDT (Single Pole Double Throw) switch. The

antenna filter blocks unwanted signals in receive mode and suppresses harmonics in the transmit mode. The filter can be either

a discrete component or fully integrated in ceramic substrate. The SPDT switch isolates the transmit path and the receive path

and thus impedance can be matched for entire signal path. A matching circuit is placed between LNA_IN pin and SPDT switch

to match the 50 ohm source to the complex input impedance of the LNA. Another external matching circuit is required at

PA_OUT to transfer maximum power to the antenna.

Unidirectional interface

The interface connections for unidirectional mode are shown as follows: the unidirectional interface can be split into two

subsections: RF data and control path, register control interface. In RF interface, ten signals are used in the RF data and control

path, and four in the register control interface.

All of the signals are unidirectional.

The unidirectional interface requires that the PT8R2401 control registers interface to the Baseband via an IEEE 1149.1 JTAG

interface. The unidirectional interface requires that the Baseband portion of the interface is referenced to a Baseband generated

clock.

Transmit Operation In Unidirectional Interface

The primary signal for data transmit is TXACTIVE signal. The actual data transmission starts after TXDATA_EN provided by

baseband. During transmit mode,

DATACLK is sent from PT8R2401 to baseband as a timing reference. The baseband circuit transmits data to the PT8R2401 at

the falling edge of DATACLK, whereas the PT8R2401 latches the data at the rising edge of DATACLK.

The state of PT8R2401 transits from the

idle state

when the baseband drives TXACTIVE HIGH. TXACTIVE enables all the

transmit circuitry except for the final output stage. TXACTIVE is driven high at a time T

TuningTX

before the hop frequency

synthesizer has settled to allow any frequency offsets caused by the TX circuitry to be eliminated. Either when, or just before,

the TX circuitry has correctly settled on frequency, the baseband drives TXDATA_EN HIGH, which enables the PA stage, and

causes the unidirectional interface to enter the

transmit data state

. The baseband drives data to the PT8R2401 on the falling

edge of DATACLK, and the PT8R2401 reads the transmit data on the rising edge. When all the data has been transmitted, the

baseband drives TXDATA_EN and TXACTIVE LOW to disable the PA stage and return to the

idle state

.

Figure 2. Transmit procedure timing diagram in unidirectional interface

Idle

VCO Tuning

Tx-Ramp-Up

Tx-Burst

Tx-Ramp-Down

Idle

JTAG

Programming

TXACTIVE

TXDATA_EN

TXDATA

RXACTIVE

SYNCDETECT

RXDATA

DATACLK

HOP CMD

Tx DATA

t

TuningTX

t

Ramp-Up

t

Ramp-Down