![](http://datasheet.mmic.net.cn/120000/PTH05050WAZ_datasheet_3570786/PTH05050WAZ_3.png)
ELECTRICAL CHARACTERISTICS
www.ti.com............................................................................................................................................................ SLTS213E – MAY 2003 – REVISED MARCH 2009
TA = 25°C; VI = 5 V; VO = 3.3 V; CI = 100 F, CO1 = 0 F, CO2 = 0 F, and Io = Iomax (unless otherwise stated)
PARAMETER
TEST CONDITIONS
PTH05050W
UNIT
MIN
TYP
MAX
IO
Output current
0.8 V
≤ VO ≤ 3.6 V
85°C, natural convection
0
6(1)
A
VI
Input voltage range
Over IO range
4.5
5.5
V
VOadj
Output adjust range
Over IO range
0.8
3.6
V
VOtol
Set-point voltage tolerance
±2(2)
%Vo
ΔRegtemp
Temperature variation
–40°C < TA < 85°C
±0.5
%Vo
ΔRegline
Line regulation
Over VI range
±10
mV
ΔRegload
Load regulation
Over IO range
±12
mV
ΔRegtot
Total output variation
Includes set-point, line, load, –40°C
≤ TA ≤ 85°C
±3(2)
%Vo
RSET = 698 , Vo = 3.3 V
95%
RSET = 2.21 k, Vo = 2.5 V
93%
RSET = 4.12 k, Vo = 2.0 V
91%
η
Efficiency
IO = 4 A
RSET = 5.49 k, Vo = 1.8 V
90%
RSET = 8.87 k, Vo = 1.5 V
89%
RSET = 17.4 k, Vo = 1.2 V
87%
RSET = 36.5 k, Vo = 1.0 V
85%
Vr
Vo ripple (pk-pk)
20 MHz bandwidth, Co2 = 10 F ceramic
20(3)
mVpp
IOtrip
Over-current threshold
Reset, followed by auto-recovery
12
A
ttr
1 A/s load step,
Recovery time
70
Sec
Transient response
50 to 100% IOmax,
Vo over/undershoot
100
mV
ΔVtr
CO1 = 100 F
IILtrack
Track input current (pin 2)
Pin to GND
–130(4)
A
dVtrack/dt
Track slew rate capability
CO ≤ CO(max)
1
V/ms
VI increasing
4.3
4.45
UVLO
Under-voltage lockout
V
VI decreasing
3.4
3.7
VIH
Input high voltage, Referenced to GND
Open(4)
V
VIL
Inhibit Control (pin 4)
Input low voltage, Referenced to GND
–0.2
0.6
IIL inhibit
Input low current, Pin 4 to GND
130
A
Iin inh
Input standby current
Inhibit (pin 4) to GND, Track (pin 2) open
10
mA
f s
Switching frequency
Over VI and IO ranges
550
600
650
kHz
CI
External input capacitance
100(5)
F
Non-ceramic
0
100(6)
3300(7)
Capacitance value
F
CO1, CO2
External output capacitance
Ceramic
0
300
Equivalent series resistance (non-ceramic)
4(8)
m
6
MTBF
Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
106 Hrs
(1)
No derating is required when the module is soldered directly to a 4-layer PCB with 1 oz. copper.
(2)
The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1% with 100 ppm/°C or better temperature stability.
(3)
The pk-pk output ripple voltage is measured with an external 10 F ceramic capacitor. See the standard application schematic.
(4)
This control pin has an internal pull-up to the input voltage. If it is left open-circuit the module will operate when input power is applied. A
small, low leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an
external pull-up on this pin. For further information, consult the related application note.
(5)
A 100 F input capacitor are required for proper operation. The capacitor must be rated for a minimum of 300 mA rms of ripple current.
(6)
An external output capacitor is not required for basic operation. Adding 100 F of distributed capacitance at the load will improve the
transient response.
(7)
This is the calculated maximum. The minimum ESR limitation will often result in a lower value. When controlling the Track pin using a
voltage supervisor, CO(max) is reduced to 2200 F. Consult the application notes for further guidance.
(8)
This is the typical ESR for all the electrolytic (non-ceramic) output capacitance. Use 7 m
as he minimum when using max-ESR values
to calculate.
Copyright 2003–2009, Texas Instruments Incorporated
3