參數(shù)資料
型號(hào): PTN3392BS/FX
廠商: NXP SEMICONDUCTORS
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220, SOT619-1, HVQFN-48
文件頁(yè)數(shù): 5/29頁(yè)
文件大小: 641K
代理商: PTN3392BS/FX
PTN3392
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 July 2010
13 of 29
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
7.6 Triple 8-bit video DACs and VGA outputs
The triple 8-bit video DACs output a 700 mV (peak-to-peak) analog video output signal
into 37.5
Ω load, as is the case of a doubly terminated 75 Ω cable. The DAC is capable of
supporting the maximum pixel rate supported by a two-lane DP link (240 MHz).
The PTN3392 generates the RGB video timing and synchronization signals, RGB signals
are then sent to the DACs for conversion to analog signals.
7.6.1 DAC reference resistor
An external reference resistor must be connected between pin RSET and analog ground.
This resistor sets the reference current which determines the analog output level, and is
specified as 1.2 k
Ω with a 1 % tolerance. This value allows a 0.7 V (peak-to-peak) output
into a 37.5
Ω load, such as a double-terminated 75 Ω coaxial cable.
8.
Power-up and reset
PTN3392 has built-in power-on reset circuitry which automatically sequences the part
through reset and initialization.
For proper behavior, a capacitor should be connected from the RESET_N pin to ground to
slow down the internal reset pulse; 1
μF capacitance is recommended.
Before link is established, the PTN3392 holds VSYNC and HSYNC signals HIGH and
blanks the RGB signals.
While the PTN3392 performs initialization,
The HPD signal is driven LOW, to indicate to the DisplayPort source that the
PTN3392 is not ready for link communication
The RED, GRN, BLU and complementary outputs (RED_N, GRN_N, BLU_N) are
disabled
The VSYNC and HSYNC outputs are driven HIGH
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