參數(shù)資料
型號： PTN3392BS/FX
廠商： NXP SEMICONDUCTORS
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQCC48
封裝： 7 X 7 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220, SOT619-1, HVQFN-48
文件頁數(shù)： 9/29頁
文件大?。?/td> 641K
代理商： PTN3392BS/FX
PTN3392
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 15 July 2010
17 of 29
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
12. Characteristics
12.1 Current consumption, power dissipation and thermal characteristics
12.2 DisplayPort receiver main link
[1]
Range is nominal
±350 ppm. DisplayPort link RX does not require local crystal for link clock generation.
[2]
Up to 0.5 % down spread is supported. Modulation frequency range of 30 kHz to 33 kHz must be supported.
Table 7.
Current consumption, power dissipation and thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD
supply current
normal operation,
UXGA / 162 MHz pixel clock
-180
-mA
IDD(stb)
standby supply current
Standby mode
-
12
-
mA
P
power dissipation
normal operation,
UXGA / 162 MHz pixel clock
-600
-mW
Rth(j-a)
thermal resistance from junction
to ambient
in free air for SOT619-1
-
35
-
K/W
RPU
pull-up resistance
RESET_N pin; 0 V
≤ V
I ≤ VDD
44
66
95
k
Ω
Rpd
pull-down resistance
S0 to S3 pins; 0 V
≤ V
I ≤ VDD
44
66
95
k
Ω
Table 8.
DisplayPort receiver main link characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
UI
unit interval
for high bit rate
(2.7 Gbit/s per lane)
370
-
ps
for low bit rate
(1.62 Gbit/s per lane)
617
-
ps
Δf
DOWN_SPREAD
link clock down spreading
[2] 0.0-
0.5%
VRX_DIFFp-p
differential input peak-to-peak
voltage
at RX package pins
for high bit rate
[3] 120
-
mV
for reduced bit rate
-
mV
tRX_EYE_CONN
receiver eye time at RX-side
connector pins
for high bit rate
[4] 0.51
-
UI
for reduced bit rate
-
UI
tRX_EYE_CHIP
receiver eye time at RX
package pins
for high bit rate
[4] 0.47
-
UI
for reduced bit rate
-
UI
tRX_EYE_m-mJT_CHP time between jitter median and
maximum median deviation
(package pins)
for high bit rate
-
0.265
UI
for reduced bit rate
-
0.39
UI
VRX_DC_CM
RX DC common mode voltage
2.0
V
IRX_SHORT
RX short-circuit current limit
50
mA
LRX_SKEW
total skew
inter-pair; lane-to-lane skew
at RX package pins
-
5200
ps
lane intra-pair skew at RX
package pins;
for high bit rate
-
100
ps
for reduced bit rate
-
300
ps
fRX_TRACKING_BW
jitter tracking bandwidth
-
MHz
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參數(shù)描述
PTN3393BS/F1Y 制造商:NXP Semiconductors 功能描述:PTN3393BS/HVQFN40/REEL13DP//F1 - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC DISPLAYPORT TO VGA 40HVQFN
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