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| 型號： | PTPS659101A1RSL |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48 |
| 文件頁數(shù)： | 72/89頁 |
| 文件大?。?/td> | 941K |
| 代理商： | PTPS659101A1RSL |
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PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
Table 63. SLEEP_KEEP_LDO_ON_REG
Address Offset
0x41
Physical Address
Instance
Description
When corresponding control bit=0 in EN1/2_ LDO_ASS register (default setting): Configuration Register
keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.
When control bit=1, LDO regulator full load capability (ACTIVE mode) is maintained during device
SLEEP state.
When control bit=0, the LDO regulator is set or stay in low power mode during device SLEEP state(but
then supply state can be overwritten programming ST[1:0]). Control bit value has no effect if the LDO
regulator is off.
When corresponding control bit=1 in EN1/2_ LDO_ASS register: Configuration Register setting the LDO
regulator state driven by SCLSR_EN1/2 signal low level (when SCLSR_EN1/2 is high the regulator is
on, full power):
- the regulator is set off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)
- the regulator is set in low power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON
register
Type
RW
7
6
5
4
3
2
1
0
VPLL_KEEPON
VDIG2_KEEPON
VDIG1_KEEPON
VMMC_KEEPON
VDAC_KEEPON
VAUX2_KEEPON
VAUX1_KEEPON
VAUX33_KEEPON
Bits
Field Name
Description
Type
Reset
7
VDAC_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
RW
0
is low
6
VPLL_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
RW
0
is low
5
VAUX33_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
RW
0
is low
4
VAUX2_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
RW
0
is low
3
VAUX1_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
RW
0
is low
2
VDIG2_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
RW
0
is low
1
VDIG1_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
RW
0
is low
0
VMMC_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1/2
RW
0
is low
Table 64. SLEEP_KEEP_RES_ON_REG
Address Offset
0x42
Physical Address
Instance
Description
Configuration Register keeping, during the SLEEP state of the device (but then supply state can be
overwritten programming ST[1:0]):
- the full load capability of LDO regulator (ACTIVE mode),
- The PWM mode of DCDC converter
- 32KHz clock output
- Register access though I2C interface (keeping the internal high speed clock on)
- Die Thermal monitoring on
Control bit value has no effect if the resource is off.
Type
RW
74
Copyright 2010, Texas Instruments Incorporated
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