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參數(shù)資料
| 型號(hào)： | PTPS659101A1RSL |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 6 X 6 MM, 1 MM HEIGHT, GREEN, PLASTIC,VQFN-48 |
| 文件頁數(shù)： | 79/89頁 |
| 文件大?。?/td> | 941K |
| 代理商： | PTPS659101A1RSL |
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PRODUCTPREVIEW
SWCS046C – MARCH 2010 – REVISED JUNE 2010
www.ti.com
Table 71. EN3_LDO_ASS_REG
Address Offset
0x49
Physical Address
Instance
Description
Configuration Register setting the LDO regulators, driven by the EN3 signal.
When control bit = 1, LDO regulator state is driven by the EN3 control signal and is also defined though
SLEEP_KEEP_LDO_ON register setting:
When EN3 is high the regulator is on,
When EN3 is low:
- the regulator is off if its corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low power mode if its corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state.
Type
RW
7
6
5
4
3
2
1
0
VDAC_EN3
VPLL_EN3
VAUX33_EN3
VAUX2_EN3
VAUX1_EN3
VDIG2_EN3
VDIG1_EN3
VMMC_EN3
Bits
Field Name
Description
Type
Reset
7
VDAC_EN3
Setting supply state control though EN3 signal
RW
0
6
VPLL_EN3
Setting supply state control though EN3 signal
RW
0
5
VAUX33_EN3
Setting supply state control though EN3 signal
RW
0
4
VAUX2_EN3
Setting supply state control though EN3 signal
RW
0
3
VAUX1_EN3
Setting supply state control though EN3 signal
RW
0
2
VDIG2_EN3
Setting supply state control though EN3 signal
RW
0
1
VDIG1_EN3
Setting supply state control though EN3 signal
RW
0
VMMC_EN3
Setting supply state control though EN3 signal
RW
0
Table 72. SPARE_REG
Address Offset
0x4A
Physical Address
Instance
Description
Spare functional register
Type
RW
7
6
5
4
3
2
1
0
SPARE
Bits
Field Name
Description
Type
Reset
7:0
SPARE
Spare bits
RW
0x00
Table 73. INT_STS_REG
Address Offset
0x50
Physical Address
Instance
Description
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
80
Copyright 2010, Texas Instruments Incorporated
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