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參數(shù)資料
| 型號： | Q67101-H5173-A701 |
| 廠商： | SIEMENS AG |
| 英文描述： | DDC-PLUS-Deflection Controller |
| 中文描述： | DDC的加偏轉(zhuǎn)控制器 |
| 文件頁數(shù)： | 18/39頁 |
| 文件大?。?/td> | 199K |
| 代理商： | Q67101-H5173-A701 |
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SDA 9362
Semiconductor Group
18
1998-02-01
NSA:
No self adaptation
0:
self adaptation on
1:
self adaptation off
STE:
Scan time enable
0:
control items for vertical scan width 0 and width 1 are disabled
1:
control items for vertical scan width 0 and width 1 are enabled
GBE:
Guard band enable
0:
control item for guard band is disabled
1:
control item for guard band is enabled
SRSE:
Start reduced scan enable
0:
control item for start reduced scan is disabled
1:
control item for start reduced scan is enabled
SSE:
Start scan enable
0:
control item for start vertical scan is disabled
1:
control item for start vertical scan is enabled
BSE:
Blanking select enable
0:
control items for blanking times are disabled
1:
control items for blanking times are enabled
The
Vertical Sync Control Byte
includes the following bits:
VBLE:
Vertical blanking extension
(this bit does not change the VBL component at output SCP, only the
trailing edge of VBLE is affected)
0:
output VBLE has the same timing as VBL component at SCP
1:
output VBLE is 6 lines longer than VBL component at SCP
SSC:
Sandcastle without VBL
0:
output SCP with VBL component
1:
output SCP without VBL component
X
VBLE
SSC
X
NI
X
X
X
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