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參數(shù)資料
| 型號(hào)： | Q67101-H6864 |
| 廠商： | SIEMENS AG |
| 英文描述： | Joint Audio Decoder-Encoder for Analog Videophone JADE AN |
| 中文描述： | 聯(lián)合音頻解碼器為模擬可視電話編碼玉安 |
| 文件頁(yè)數(shù)： | 49/272頁(yè) |
| 文件大?。?/td> | 4055K |
| 代理商： | Q67101-H6864 |
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SAB 82532/SAF 82532
HDLC/SDLC Serial Mode
Semiconductor Group
49
07.96
5
HDLC/SDLC Serial Mode
5.1
The HDLC controller of each channel can be programmed to operate in various modes,
which are different in the treatment of the HDLC frame in receive direction. Thus, the
receive data flow and the address recognition features can be performed in a very
flexible way, to satisfy almost any practical requirements.
There are 6 different operating modes which can be set via the MODE register.
Operating Modes
Auto-Mode (MODE: MDS1, MDS0 = ‘00’)
Characteristics: Window size 1, random message length, address recognition.
The ESCC2 processes autonomously all numbered frames (S-, I-frames) of an HDLC
protocol. The HDLC control field, data in the I-field of the frames and an additional status
byte are temporarily stored in the RFIFO. The HDLC control field as well as additional
information can also be read from special registers (RHCR, RSTA).
Depending on the selected address mode, the ESCC2 can perform a 2-byte or 1-byte
address recognition. If a 2-byte address field is selected, the high address byte is
compared with the fixed value FE
H
or FC
H
(group address) as well as with
two individually programmable values in RAH1 and RAH2 registers. According to the
ISDN LAPD protocol, bit 1 of the high byte address will be interpreted as
COMMAND/RESPONSE bit (C/R), dependent on the setting of the CRI bit in RAH1, and
will be excluded from the address comparison.
Similarly, two comparison values can be programmed in special registers (RAL1, RAL2)
for the low address byte. A valid address will be recognized in case the high and low byte
of the address field correspond to one of the compare values. Thus, the ESCC2 can be
called (addressed) with 6 different address combinations, however, only the logical
connection identified through the address combination RAH1, RAL1 will be processed in
the auto-mode, all others in the non auto-mode. HDLC frames with address fields that
do not match any of the address combinations, are ignored by the ESCC2.
In the case of a 1-byte address, RAL1 and RAL2 will be used as comparison registers.
According to the X.25 LAPB protocol, the value in RAL1 will be interpreted as
COMMAND and the value in RAL2 as RESPONSE.
In version 2 and upwards the address bytes can be masked to allow selective broadcast
frame recognition. For further information see
chapter 5.4.10
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Q67103-H6594 | Memory Time Switch Extended Large MTSXL |
| Q67106-A8315 | Dimmer IC for Halogen Lamps |
| Q67106-H5157 | Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder |
| Q67106-H5163 | VPS / PDC-plus Decoder |
| Q67106-H5183 | VPS-Decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Q67103-H6594 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| Q67106-A8315 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Dimmer IC for Halogen Lamps |
| Q67106-H5157 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder |
| Q67106-H5163 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS / PDC-plus Decoder |
| Q67106-H5183 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS-Decoder |
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