參數(shù)資料
型號(hào)： QL1P100-6PU86M
廠商： QUICKLOGIC CORP
元件分類： FPGA
英文描述： FPGA, 640 CLBS, 100000 GATES, PBGA86
封裝： 6 X 6 MM, 1.20 MMHEIGHT, 0.50 MM PITCH, TFBGA-86
文件頁(yè)數(shù)： 10/44頁(yè)
文件大?。?/td> 1101K
代理商： QL1P100-6PU86M
2010 QuickLogic Corporation
QuickLogic PolarPro Device Data Sheet — 86-Pin TFBGA QL1P100
18
Programmable Weak Keeper, Pull-Up, and Pull-Down
A programmable Weak Keeper, Pull-Up or Pull-Down controller is also available on each General Purpose I/O
bank. When implementing the Weak Keeper, Pull-Up, and Pull-Down functions, each I/O can be configured
separately. The I/O Weak Pull-Up and Pull-Down eliminates the need for external resistors. When PBK=1 the
keeper block is placed into keeper mode. In the keeper mode, the pad pin (if the driver is tristated), will be kept
at whichever level it was last forced, either by the driver itself, or by an external driver.
Programmable Drive Strength
Every GPIO has independent drive strength control. Twelve different drive strength levels are available for
designers to choose from. For additional information about corresponding drive strength see DC
Programmable Slew Rate
Each I/O has programmable slew rate capability. The PolarPro GPIOs allow up to four different slew rate
speeds (slow, fast, vfast, and wow). Slower slew rates can be used to reduce noise caused by I/O switching.
I/O interface standards are programmable on a per bank basis. Table 19 illustrates the I/O bank
configurations available. Each I/O bank is independent of other I/O banks and each I/O bank has its own
VCCIO supply inputs. A mixture of different I/O standards can be used on a PolarPro device. However, there
is a limitation as to which I/O standards can be supported within a given bank. Only standards that share a
common VCCIO can be shared within the same bank (e.g., PCI and LVTTL).
Table 18: Weak Pull-Up, and Pull-Down Controller
PBK
PBD
PBE
Function
0
Tristate (floating)
0
1
Weak Pull-Down
0
1
Weak Pull-Up
1
X
Weak Keeper (retains state)
0
1
0
Reserved
Table 19: I/O Standards and Applications
I/O Standard
VCCIO Voltage
Application
LVTTL
3.3 V
General Purpose
LVCMOS25
2.5 V
General Purpose
LVCMOS18
1.8 V
General Purpose
PCI
3.3 V
PCI Bus Applications
相關(guān)PDF資料
PDF描述
QL1P100-6PUN86C FPGA, 640 CLBS, 100000 GATES, PBGA86
QL1P100-6PUN86I FPGA, 640 CLBS, 100000 GATES, PBGA86
QL1P100-6PUN86M FPGA, 640 CLBS, 100000 GATES, PBGA86
QL1P100-7PU86C FPGA, 640 CLBS, 100000 GATES, PBGA86
QL1P100-7PU86I FPGA, 640 CLBS, 100000 GATES, PBGA86
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
QL-1RED 制造商:Panduit Corp 功能描述:
QL-1WHT 制造商:Panduit Corp 功能描述:
QL-1YEL 制造商:Panduit Corp 功能描述:B-SI
QL2003 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
QL2003-0PF100C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*