參數(shù)資料
型號(hào): QL24x32B
廠商: QuickLogic Corp.
英文描述: pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs(pASIC 1系列 ViaLink技術(shù)超高速CMOS現(xiàn)場(chǎng)可編程門陣列)
中文描述: 帕希奇1家庭技術(shù)ViaLink?技術(shù)非常高速的CMOS的FPGA(帕希奇1系列技術(shù)ViaLink?技術(shù)超高速的CMOS現(xiàn)場(chǎng)可編程門陣列)
文件頁(yè)數(shù): 1/4頁(yè)
文件大小: 186K
代理商: QL24X32B
pASIC 1 Family
ViaLink Technology
Very-High-Speed CMOS FPGAs
4-1
Very High Speed
– ViaLink
metal-to-metal, programmable-via
antifuse technology ensures useful internal logic function speeds at
over 100 MHz, and logic cell delays of under 2 ns.
High Usable Density
– Up to 8,000 usable ASIC gates, equivalent to
14,000 usable programmable logic (PLD) gates.
Low Power/ 3.3 Volt Supply
– Stand-by current typically 2 mA with
5.0 Volt supply and less than 1 mA with 3.3 Volt supply.
Flexible FPGA Architecture
– The pASIC 1 logic cell supports
efficient, high-speed arithmetic, counter, data path, state machine and
random logic applications with up to 14-input wide gates.
Low-Cost, Easy-to-Use Design Tools
– Designs entered and
simulated using QuickLogic’s QuickWorks toolkit or third-party
CAE tools. Fast, fully automatic place and route on PC and
workstation platforms.
QL8x12B
1,000
2,000
96
160
64
44 PLCC
68 PLCC
100 TQFP
QL12x16B
2,000
4,000
192
280
88
68 PLCC
84 PLCC
84 CPGA
100 TQFP
QL16x24B
4,000
7,000
384
506
122
84 PLCC
100 TQFP
144 TQFP
144 CPGA
160 CQFP
QL24x32B
8,000
14,000
768
948
180
144 TQFP
208 PQFP
208 CQFP
ASIC Gates
Usable PLD Gates
Logic Cells
Max. Flip-Flops
Maximum I/Os
Packages
p
4
FAMILY
HIGHLIGHTS
TABLE 1
pASIC 1 Device
Family
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