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參數(shù)資料
| 型號： | QL4090-2CG256M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| 中文描述： | 9.0萬門QuickRAM可用PLD的結合性能，密度和嵌入式內存 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 405K |
| 代理商： | QL4090-2CG256M |
54
Preliminary
8-54
Military QuickRAM
Rev A
QL4036 Clock Cells
I/O Cell Input Delays
I/O Cell Output Delays
Notes:
[5] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25
°
C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
[7] The array distributed networks consist of 56 half columns and the global distributed networks consist of
60 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 12 loads per half column. The global clock has up
to 15 loads per half column.
[8] The following loads are used for tPXZ:
Symbol
Parameter
Propagation Delays (ns)
Loads per Half Column
[7]
3
4
1.3
1.3
0.7
0.7
0.9
0.9
1
2
8
10
1.6
0.7
1.2
12
1.7
0.7
1.3
15
1.8
0.7
1.4
tACK
tGCKP
tGCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
1.2
0.7
0.8
1.2
0.7
0.8
1.5
0.7
1.1
Symbol
Parameter
Propagation Delays (ns)
Fanout
[5]
2
3
1.6
1.8
3.1
3.1
0.0
0.0
1.0
1.2
0.9
1.1
2.3
2.3
0.0
0.0
1
4
8
10
3.6
3.1
0.0
3.0
2.9
2.3
0.0
tI/O
TISU
TIH
TlOCLK
TlORST
TlESU
TlEH
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
1.3
3.1
0.0
0.7
0.6
2.3
0.0
2.1
3.1
0.0
1.5
1.4
2.3
0.0
3.1
3.1
0.0
2.5
2.4
2.3
0.0
Symbol
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
50
75
2.5
3.1
2.6
3.2
1.7
2.2
2.0
2.6
30
2.1
2.2
1.2
1.6
2.0
1.2
100
3.6
3.7
2.8
3.1
150
4.7
4.8
3.9
4.2
TOUTLH
TOUTHL
TPZH
TPZL
TPHZ
TPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [8]
Output Delay Low to Tri-State [8]
5 pF
1K
5 pF
1K
tPHZ
tPLZ
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相關代理商/技術參數(shù) |
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|---|---|
| QL4090-2CG256M/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| QL4090-2CG456M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| QL4090-2CG456M/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| QL4090-2CG84M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
| QL4090-2CG84M/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM |
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