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參數(shù)資料
| 型號(hào)： | QL5064-33APB484I |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁數(shù)： | 28/37頁 |
| 文件大?。?/td> | 806K |
| 代理商： | QL5064-33APB484I |
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QL5064 QuickPCI Data Sheet
22.0 QL5064 Pin Type Descriptions
The QL5064 Device Pins are indicated in the table below. These are pins on the device, some of which
connect to the PCI bus, and others that are programmable as user I/O.
NOTE:
Signal names which end with the character ‘N’ should be considered active-low
(for example, Mst_IRDYN).
Table 16: Pin Type Descriptions
Type
Description
IN
Input. A standard input-only signal
OUT
Totem pole output. A standard active output driver
T/S
Tri-state. A bi-directional, tri-state input/output pin
S/T/S
Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven high for
at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the PCI system central
resource to sustain the inactive state once the active driver has released the signal.
O/D
Open Drain. Allows multiple devices to share this pin as a wired-or.
Table 17: Pin / Bus Names and Functions
Pin/Bus
Name
Type
Function
VCC
IN
Supply pin. Tie to 3.3V supply.
VCCIO
IN
Supply pin for I/O. Set to 3.3V for 3.3V I/O, 5V for 5.0V compliant I/O
GND
IN
Ground pin. Tie to GND on the PCB.
T/GND
IN
Thermal Ground. Used to dissipate heat from the device. Tie to GND on
the PCB.
I/O
T/S
Programmable Input/Output/Tri-State/Bi-directional Pin.
I/GCLK
IN
Programmable Input-Only or Global Clock Pin. Tie to VCC or GND if unused.
I/ACLK
IN
Programmable Input-Only or Array Clock Pin. Tie to VCC or GND if unused.
TDI
IN
JTAG Data In. Tie to VCC if unused.
TDO
OUT
JTAG Data Out. Leave unconnected if unused.
TCL
IN
JTAG Clock. Tie to GND if unused.
TMS
IN
JTAG Test Mode Select. Tie to VCC if unused.
TRSTB
IN
JTAG Reset. Tie to GND if unused.
STM
IN
QuickLogic Reserved pin. Tie to GND on the PCB.
FLOAT
OUT
Test Data Out pin for QuickLogic use only. Must be isolated and floating at
all times
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