- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361297 > QL8X12B-PQ208M883C (Electronic Theatre Controls, Inc.) Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA PDF資料下載
參數(shù)資料
| 型號： | QL8X12B-PQ208M883C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA |
| 中文描述： | 軍事5.0V帕希奇1家庭-非常高速的CMOS的FPGA |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 325K |
| 代理商： | QL8X12B-PQ208M883C |
8-21
Military 5.0V pASIC 1 Family
QL24x32B
A
C CHARACTERISTICS at VCC = 5V, TA = 25
°
C (K = 1.00)
Logic Cell
Input Cells
Output Cell
Notes:
[6] See High Drive Buffer Table for more information.
[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of
half columns used does not affect clock buffer delay.
[8] The following loads are used for tPXZ:
QL24
X
32B
Propagation Delays (ns)
Fanout
2
3
2.1
2.7
2.1
2.1
0.0
0.0
1.5
1.9
2.0
2.0
2.0
2.0
2.2
2.7
1.9
2.3
1.9
1.9
1.8
1.8
Symbol
Parameter
1
4
8
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay [5]
Setup Time [5]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
1.7
2.1
0.0
1.0
2.0
2.0
1.7
1.5
1.9
1.8
3.3
2.1
0.0
2.7
2.0
2.0
3.3
2.8
1.9
1.8
5.5
2.1
0.0
4.9
2.0
2.0
5.5
4.6
1.9
1.8
Symbol
Parameter
Propagation Delays (ns)
[4]
1
2
3
4
8
12
5.8
6.0
6.7
3.3
2.0
2.0
16
6.5
6.7
8.5
3.4
2.0
2.0
tIN
tINI
tIO
tGCK
tGCKHI
tGCKLO
High Drive Input Delay [6]
High Drive Input, Inverting Delay [6]
Input Delay (bidirectional pad)
Clock Buffer Delay [7]
Clock Buffer Min High [7]
Clock Buffer Min Low [7]
3.1
3.3
1.4
2.7
2.0
2.0
3.2
3.4
1.9
2.8
2.0
2.0
3.3
3.5
2.3
2.9
2.0
2.0
3.4
3.6
3.0
3.0
2.0
2.0
4.4
4.6
4.8
3.1
2.0
2.0
Propagation Delays (ns)
[4]
Output Load Capacitance (pF)
50
75
3.3
3.8
3.6
4.5
2.6
3.1
3.3
4.1
Symbol
Parameter
30
2.7
2.8
2.1
2.6
2.9
3.3
100
4.3
5.3
3.7
4.9
150
5.4
6.9
4.8
6.5
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-state [8]
Output Delay Low to Tri-state [8]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL8x12B | pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs(pASIC 1系列 ViaLink技術(shù)超高速CMOS現(xiàn)場可編程門陣列) |
| QL12x16B | pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs(pASIC 1系列 ViaLink技術(shù)超高速CMOS現(xiàn)場可編程門陣列) |
| QL16x24B | pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs(pASIC 1系列 ViaLink技術(shù)超高速CMOS現(xiàn)場可編程門陣列) |
| QL24x32B | pASIC 1 Family ViaLink Technology Very-High-Speed CMOS FPGAs(pASIC 1系列 ViaLink技術(shù)超高速CMOS現(xiàn)場可編程門陣列) |
| QL901M-6PS680 | SOCKET, PCB, RIGHT ANGLE, 26WAY; Connector type:Wire-to-Board; Gender:Socket; Ways, No. of:26; Pitch, lead:2.54mm; Termination method:Solder; Material, contact:Copper alloy; Plating, contact:0.3u Gold over 2u Nickel; Rows, No. of:2; RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL8X12B-XPF100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL8X12B-XPF100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL8X12B-XPL44C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL8X12B-XPL44I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL8X12B-XPL68C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
發(fā)布緊急采購，3分鐘左右您將得到回復。