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參數(shù)資料
| 型號(hào)： | QS5917T-100TQ |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | GIGATRUE 550 CAT6 YELLOW STRANDED BULK 1000FT |
| 中文描述： | 5917 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | QSOP-28 |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大小： | 62K |
| 代理商： | QS5917T-100TQ |
INDUSTRIAL TEMPERATURE RANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
5
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
F
I
t
PWC
D
H
Description
Min.
—
14
2
25
Max.
3
F
2XQ
—
75
Unit
ns
MHz
ns
%
Maximuminput rise and fall times, 0.8V to 2V
Input Clock Frequency, SYNC
0
, SYNC
1 (1)
Input clock pulse, HIGH or LOW
Duty cycle, SYNC
0
, SYNC
1
NOTE:
1. The F
I
specification is based on Q output feedback. See the Frequency Selection Table for more detail on allowable SYNC input frequencies for different feedback combinations.
SWITCHING CHARACTERISTICS
(1)
Symbol
t
SKR
Parameter
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/2
(1)
Min.
—
Max.
350
Unit
ps
t
SKF
Output Skew Between Falling Edges, Q
0
-Q
4
(1)
—
350
ps
t
SKALL
Output Skew, All Outputs
(1)
—
500
ps
t
PW
Pulse Width, Q
5,
2xQ outputs
T
CY
/2
0.65
T
CY
/2
0.5
T
CY
/2 + 0.65
ns
t
PW
Pulse Width, Q
0
-Q
4
, Q/2
outputs
(1)
T
CY
/2 + 0.5
ns
t
J
Cycle-to-Cycle Jitter, 33MHz
(3)
—
0.25
ns
t
PD
SYNC Input to Feedback Delay, 28MHz
SYNC Input to Feedback Delay, 33MHz, 50
to 1.5V
100
100
400
ps
t
PD
400
ps
t
LOCK
SYNC to Phase Lock
Output Enable Time,
RST
LOW to HIGH
(2)
—
10
ms
t
PZH
t
PZL
0
7
ns
t
PHZ
t
PLZ
Output Disable Time,
RST
HIGH to LOW
(2)
0
6
ns
t
R,
t
F
Output Rise/Fall Times, 0.8V to 2V
0.4
1.5
ns
NOTES:
1. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
2. Measured in open loop mode PLL_EN = 0.
3. Jitter is characterized using an oscilloscope. Measurement is taken one cycle after jitter. Jitter is characterized but not tested. See FREQUENCY SELECTION TABLE for information
on proper FREQ_SEL level for specified input frequencies.
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相關(guān)代理商/技術(shù)參數(shù) |
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| QS5917T-100TQG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CLK DRVR PLL, FILTER RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| QS5917T-100TQG8 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 28-Pin QSOP T/R 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28QSOP - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:CLK DRVR PLL, FILTER |
| QS5917T-132TJ | 制造商:Integrated Device Technology Inc 功能描述:IDT QS5917T-132TJ PLL - Rail/Tube |
| QS5917T-132TJ8 | 制造商:Integrated Device Technology Inc 功能描述:Clock Generators & Support Products CLK DRVR PLL, FILTER |
| QS5917T-132TJG | 制造商:Integrated Device Technology Inc 功能描述:IDT QS5917T-132TJG PLL - Rail/Tube |
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