參數(shù)資料
型號: QS5917T-70TJ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
中文描述: 5917 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 2/7頁
文件大?。?/td> 62K
代理商: QS5917T-70TJ
INDUSTRIAL TEMPERATURE RANGE
2
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, V
IN
= 0V)
Symbol
Rating
Max
Unit
V
V
V
W
°C
Supply Voltage to Ground
DC Input Voltage V
IN
AC Input Voltage (pulse width
20ns)
MaximumPower Dissipation (T
A
= 85°C)
Storage Temperature Range
–0.5 to +7
–0.5 to +7
–3
1.2
–65 to +150
T
STG
ABSOLUTE MAX IMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
20
19
18
15
16
23
22
24
21
17
V
DD
GND
PLL_EN
GND
Q/2
Q
3
LOCK
V
DD
2xQ
Q
1
25
28
27
26
V
DD
Q
2
GND
Q
4
2
3
1
9
10
AV
DD
NC
RST
SYNC
0
FEEDBACK
AGND
5
6
7
4
8
Q
5
11
12
FREQ_SEL
SYNC
1
GND
V
DD
REF_SEL
13
14
Q
0
GND
QSOP
TOP VIEW
PLCC
TOP VIEW
R
V
D
Q
5
G
Q
4
V
D
2
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
P
G
Q
1
V
D
Q
0
G
F
FEEDBACK
REF_SEL
SYNC
0
AV
DD
NC
AGND
SYNC
1
28
4
3
2
1
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
QSOP
PLCC
Parameter
C
IN
Typ.
3
Max.
4
Typ.
4
Max.
6
Unit
pF
C
OUT
7
9
8
10
pF
相關(guān)PDF資料
PDF描述
QS5917T-70TQ LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
QS5919-55TQX Eight Distributed-Output Clock Driver
QS5919-70TJ Eight Distributed-Output Clock Driver
QS5919-70TJX Eight Distributed-Output Clock Driver
QS5919-70TQ Eight Distributed-Output Clock Driver
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