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參數(shù)資料
| 型號： | QS5919T100Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | QSOP-28 |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 129K |
| 代理商： | QS5919T100Q |
8
INDUSTRIAL TEMPERATURE RANGE
QS5919T
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5919T
provides for replication of incomng SYNC clock signals. Any manipulation
of that signal, such as frequency multiplying or inversion is performed by
digital logic following the PLL (see the block diagram). The key advantage
SIMPLIFIED DIAGRAM OF QS5919T FEEDBACK
The phase difference between the output and the input frequencies
feeds the VCO which drives the outputs. Whichever output is fed back, it
will stabilize at the same frequency as the input. Hence, this is a true
negative feedback closed loop system In most applications, the output will
optimally have zero phase shift with respect to the input. In fact, the internal
loop filter on the QS5919T typically provides within 150ps of phase shift
between input and output.
of the PLL circuit is to provide an effective zero propagation delay between
the output and input signals. In fact, adding delay circuits in the feedback
path, ‘propagation delay’ can even be negative! A simplified schematic
of the QS5919T PLL circuit is shown below.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
be advanced by the amount of delay in the feedback path. All other outputs
will retain their proper relationships to that output.
Q
Q/
2
Q
VCO
/2
/2
PHASE
DETECTOR
INPUT
2xQ
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| QS5919T133J | LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5919T133Q | LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5919T-100TJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| QS5919T-100TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| QS5919T133J | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5919T133Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5919T-133TJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
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