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參數(shù)資料
| 型號(hào)： | QS5919T55J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 2/9頁(yè) |
| 文件大小： | 129K |
| 代理商： | QS5919T55J |
2
INDUSTRIAL TEMPERATURE RANGE
QS5919T
LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
QSOP
TOP VIEW
PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
, AV
DD
V
IN
Rating
Max.
–0.5 to +7
–0.5 to +7
655
770
–65°C to +150°C
Unit
V
V
mW
mW
°C
Supply Voltage to Ground
DC Input Voltage V
IN
MaximumPower
Dissipation (T
A
= 85°C)
Storage Temperature Range
QSOP
PLCC
T
STG
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25
°
C, f = 1MHz, V
IN
= 0V)
QSOP
PLCC
Parameter
C
IN
Typ.
3
Max.
4
Typ.
4
Max.
6
Unit
pF
20
19
18
15
16
23
22
24
21
17
V
DD
GND
PLL_EN
GND
Q/2
Q
3
LOCK
V
DD
2xQ
Q
1
25
28
27
26
V
DD
Q
2
GND
Q
4
SO28-9
2
3
1
9
10
AV
DD
PE
OE/RST
SYNC
0
FEEDBACK
AGND
5
6
7
4
8
Q
5
11
12
FREQ_SEL
SYNC
1
GND
V
DD
REF_SEL
13
14
Q
0
GND
O
V
D
Q
5
G
Q
4
V
D
2
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
P
G
Q
1
V
D
Q
0
G
F
FEEDBACK
REF_SEL
SYNC
0
AV
DD
PE
AGND
SYNC
1
28
4
3
2
1
27
26
25
24
23
22
21
20
19
5
6
7
8
9
10
11
12
13
14
15
16
17
18
J28-1
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| QS5919T55Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
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| QS5919T-70J | 制造商:Integrated Device Technology Inc 功能描述:QS5919T-70J - Bulk |
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