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參數(shù)資料
| 型號(hào)： | QS5930 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 低偏移的CMOS PLL時(shí)鐘驅(qū)動(dòng)器，帶有集成環(huán)路濾波器 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 57K |
| 代理商： | QS5930 |
1
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
R
D
Q
Q
0
R
D
Q
Q
1
R
D
Q
Q
2
R
D
Q
Q
3
R
D
Q
Q
4
R
D
Q
Q/2
0
1
1
0
/2
VCO
LOOP
FILTER
PHASE
DETECTOR
FREQ_SEL
FEEDBACK
SYNC
PLL_EN
OE/RST
Q
S EPT EMBER 2000
2000 Integrated Device Technology, Inc.
DSC-5849
c
QS5930T
INDUS T RIAL T E MPE RAT URE RANGE
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
5V operation
Q/2 output, 5 Q outputs
Useful for Pentium PowerPC, and PCI systems
Internal loop filter RC network
Low noise TTL level outputs
<250ps rising edge output skew
Balanced drive outputs ±24mA
PLL bypass feature for low frequency testing
Internal VCO/2 option for wider frequency range
Outputs tri-state and reset while OE/
RST
is low
ESD > 2000V
Latch up > -300mA
Available in QSOP package
DESCRIPTION
The QS5930T Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to a reference clock input. Six outputs
are available: Q
0
–Q
4
, Q/2. Careful layout and design ensure < 250ps
skew between the Q
0
–Q
4
, and Q/2 outputs. The QS5930T includes
an internal RC filter which provides excellent jitter characteristics and
elimnates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customzed for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5930T is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe sys-
tems. Several can be used in parallel or scattered throughout a sys-
temfor guaranteed low skew, system-wide clock distribution networks.
In the QSOP package, the QS5930T clock driver represents the best
value in small formfactor, high-performance clock management prod-
ucts.
For more information on PLL clock driver products, see Application
Note AN-227.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QS5930-50TQ | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5930-66TQ | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5930T | LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5935Q | Four Distributed-Output Clock Driver |
| QS5931-50Q | Six Distributed-Output Clock Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS593050TQ | 制造商:QS 功能描述:NEW |
| QS5930-50TQ | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 20-Pin SSOP |
| QS5930-66TQ | 制造商:Integrated Device Technology Inc 功能描述: |
| QS5930T | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5931-50Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Six Distributed-Output Clock Driver |
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