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參數(shù)資料
| 型號(hào)： | QS5LV931-50Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | QS5LV931-50Q |
4
INDUSTRIAL TEMPERATURE RANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE
Symbol
t
SKR
t
SKF
t
PW
t
J
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Parameter
(1)
Min.
—
—
Max.
300
300
Unit
ps
ps
ns
ns
ps
ms
ns
Output Skew Between Rising Edges, Q
0
-Q
4
and Q/2
(2)
Output Skew Between Falling Edges, Q
0
-Q
4
and Q/2
(2)
Pulse Width, Q
0
-Q
4
, Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter
(4)
SYNC Input to Feedback Delay
(5)
SYNC to Phase Lock
Output Enable Time, OE/
RST
LOW to HIGH
(3)
T
CY
/2
0.4
— 0.15
500
—
0
T
CY
/2 + 0.4
0.15
500
10
14
Output Disable Time, OE/
RST
HIGH to LOW
(3)
0
14
ns
Output Rise/Fall Times, 0.8V
~
2V
0.3
2
ns
NOTES:
1. See Test Loads and Waveforms for test load and termnation.
2. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. t
PD
measured at device inputs at 0.5V
DD
, Q output at 80MHz.
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