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參數(shù)資料
| 型號(hào)： | QS5LV931-50Q |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| 中文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | QSOP-20 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | QS5LV931-50Q |
7
INDUSTRIAL TEMPERATURE RANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5LV931
provides for replication of incomng SYNC clock signals. Any manipulation
of that signal, such as frequency multiplying, is performed by digital logic
following the PLL (see the block diagram). The key advantage of the PLL
SIMPLIFIED DIAGRAM OF QS5LV 931 FEEDBACK
The phase difference between the output and the input frequencies feeds
the VCO which drives the outputs. Whichever output is fed back, it will
stabilize at the same frequency as the input. Hence, this is a true negative
feedback closed loop system In most applications, the output will optimally
have zero phase shift with respect to the input. In fact, the internal loop filter
on the QS5LV931 typically provides within 150ps of phase shift between
input and output.
circuit is to provide an effective zero propagation delay between the output
and input signals. In fact, adding delay circuits in the feedback path,
‘propagation delay’ can even be negative! A simplified schematic of the
QS5LV931 PLL circuit is shown below.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
be advanced by the amount of delay in the feedback path. All other outputs
will retain their proper relationships to that output.
Q/2
Q
VCO/2
/2
PHASE
DETECTOR
INPUT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QS5LV93166Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV931-66Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV93180Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5LV931-80Q | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5U12 | 制造商:ROHM 制造商全稱:Rohm 功能描述:2.5V Drive Nch+SBD MOS FET |
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