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參數(shù)資料
| 型號： | R5107N181A-TR-FE |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, SSOP-8 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大小： | 517K |
| 代理商： | R5107N181A-TR-FE |
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R510xx
22
Manual Reset (MR) Function
By setting MR pin as "L", the output of RESETB can be forced to set "L". After pull-down the MR pin to "L", the
delay time (tMR) to the output "L" from RESETB is 1
μs as maximum. MR pin is pulled-up via the built-in resistor.
(Typ. 110k
Ω ). If MR pin voltage > VDD voltage, a current flows into MR pin. However, the current value is limit by
the pull-up resistor, therefore there is not bad impact on the operation. When the "L" signal is input to MR pin,
the discharge of CD pin capacitor (CD) starts. If the term of "L" for MR pin is short, CD will not be discharged
enough. As a result, the delay time after setting "H" for MR pin will be shorter than expected. Because of this,
confirm the operation under the same conditions as users' applications. For example, in case of CD is set at
0.1
μF, and the condition to maintain the delay time value after MR pin's returning to "H", is described as the
minimum "L" term of MR pin, or 150
μs. When MR input pulse (tMRW) is less than 3.0μs, output delay time (tPLH)
might not exist.
Power on Reset Operation with MR pin input (tPLH1 < tPLH, tMRW1 < tMRW)
VCD
VRESETB
Complete
Discharge
+VTCD
-VTCD
tPLH1
0V
tPLH
Incomplete
Discharge
tMRW
tMRW1
VMR
tMR
Inhibit (INH) Function
If INH pin is set at "L", the watchdog timer stops monitoring the clock, and the RESETB output will be
dominant by the voltage detector's operation. Therefore, if the supply voltage is set at more than the detector
threshold level, RESETB outputs "H" regardless the clock pulse. INH pin is pulled up with a resistor (Typ.110k
Ω)
internally.
RESETB Output
RESETB pin's output type is selectable either the Nch open-drain output or CMOS output. If the Nch
open-drain type output is selected, the RESETB pin is pulled up with an external resistor to an appropriate
voltage source.
Clock Pulse Input
Built-in watchdog timer is cleared with the SCK clock pulse within the watchdog timeout period.
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