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參數(shù)資料
| 型號： | R5107N181A-TR-FE |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, SSOP-8 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 517K |
| 代理商： | R5107N181A-TR-FE |
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R510xx
27
OPERATION
(1) When the power supply, VDD pin voltage becomes more than the released voltage (+VDET), after the released
delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level.
(2) After the SCK1 pulse is input, when the SCK2 pulse is input, the watchdog timer is cleared, and CTW pin
mode changes from the discharge mode to the charge mode. When the CTW pin voltage becomes higher
than Vref2H, the mode will change into the discharge mode, and next watchdog time count starts.
(3) After the SCK1 pulse is input, unless the SCK2 pulse is input, WDT will not be cleared, and during the
charging period of CTW pin, RESETB
="L".
(4) When the VDD pin becomes lower than the detector threshold voltage (-VDET), RESETB outputs "L" after the
tPHL.
(5) If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state.
(6) During the "L" period of INH pin, the voltage detector monitors the supply voltage.
(7) When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system clock, or
charge cycle to the CTW pin starts, the capacitor connected to the CTW pin is charged with the current of
setting Reset time of WDT.
(8) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared.
(9) Without the input of SCK1 pulse input, even if the SCK2 pulse is input, the WDT will not be cleared.
(10) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared.
(11) If SCK1 pulse and SCK2 pulse are input at the same time, the WDT will not be cleared.
(12) After from the discharge of the external capacitor even if the clock pulse is input during the time period "tWDI",
the clock pulse is ignored.
(13) After the SCK1 pulse is input, when the SCK2 is input, the WDT will be cleared.
(14) The WDT supervises SCK1 pulse and SCK2 pulse by turns, therefore, for example, if only SCK1 pulse is
input twice or more without SCK2 pulse, the second or later consecutive SCK1 pulse will be ignored. After
the SCK1 pulse is input, and when the SCK2 pulse is input, the WDT will be cleared. In the same way, if
only SCK2 pulse is input twice or more without SCK1 pulse, the second or later consecutive SCK2 pulse
will be ignored.
Too close timing of SCK1 pulse input and SCK2 pulse input means the rising edge interval time range from
0ns to 50ns. (Guaranteed by design, not mass production tested.)
Even if the SCK1 and SCK2 are input at almost the same time as above, the WDT will still try to supervise
these two clock by turns.
Therefore, after the SCK1 pulse is input, if SCK1 pulse and SCK2 pulse are input at almost the same time,
the WDT will be cleared. (as the status (8))
Likewise, after the SCK1 pulse and SCK2 pulse are input at almost the same time, when the SCK2 pulse is
input, the WDT will be cleared. (as the status (10))
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