參數(shù)資料
型號： R5F56218BDLD#U0
廠商： Renesas Electronics America
文件頁數(shù)： 94/148頁
文件大?。?/td> 0K
描述： MCU 32BIT FLASH 512K ROM 85TFLGA
產(chǎn)品培訓模塊： RX USB Peripheral
CAN Peripheral and API
RX 12-Bit ADC
RX Bus State Controller
RX Low Voltage Detection and Reset Sources
RX Watchdog Timer
RX 10-Bit ADC
RX 10-Bit DAC
RX Core
RX Compare Match Timer
RX DMAC
特色產(chǎn)品： RX600 Series Microcontrollers
標準包裝： 1
系列： RX600
核心處理器： RX
芯體尺寸： 32-位
速度： 100MHz
連通性： CAN，EBI/EMI，I²C，SCI，SPI，USB
外圍設備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 58
程序存儲器容量： 512KB（512K x 8）
程序存儲器類型： 閃存
RAM 容量： 96K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 8x10/12b，D/A 1x10b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 85-TFLGA
包裝： 托盤
R01DS0052EJ0130 Rev.1.30
Page 5 of 147
2012.01.11
RX62N Group, RX621 Group
1. Overview
Note 1. For products in the 100-pin LQFP and 85-pin TFLGA, the synchronizing frequency is 8 to 25 MHz.
Note 2. The 100-pin LQFP and 85-pin TFLGA do not support the SDRAM area controller and EXDMA controller.
Note 3. The 85-pin TFLGA does not support the port-output enabling.
Communication
function
I2C bus interfaces
2 channels (100-pin version: 1 channel)
Communications formats
I2C bus format/SMBus format
Master/slave selectable (For multi-master operation)
CAN module
1 channel
32 mailboxes
Serial peripheral
interfaces
2 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16, or
to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each
frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
Max. transfer rate
In master mode: 18 Mbps
In slave mode: 6.25 Mbps
12-bit A/D converter
10-bit A/D converter
12 bits x 1 unit (1 unit x 8 channels) or 10 bits x 2 units (2 units x 4 channels);
12- and 10-bit A/D converters can be exclusively used.
10- or 12-bit resolution
Conversion time: 1.0 s per channel (in operation with PCLK at 50 MHz)
Two operating modes
Single mode
Scan mode (one-cycle scan mode or continuous scan mode)
Sample-and-hold function
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU or
TMR), or an external trigger signal.
Self-diagnostic functions
D/A converter
2 channels (1 channel for 100-pin products)
10-bit resolution
Output voltage: 0 V to VREFH
CRC calculator
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable.
Operating frequency
8 to 100 MHz
Power supply voltage
VCC = PLLVCC = AVCC = 2.7 to 3.6V, VREFH = 2.7 to AVCC
Operating temperature
40 to +85C
Package
176-pin LFBGA (PLBG0176GA-A), 145-pin TFLGA (PTLG0145JB-A),
144-pin LQFP (PLQP0144KA-A), 100-pin LQFP (PLQP0100KB-A)*2
85-pin TFLGA (PTLG0085JA-A)*2,*3
Table 1.1
Outline of Specifications (4 / 4)
Classification
Module/Function
Description
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