Highest performance Highest integration 32-Bit Highest performance CISC 16-Bit <" />
參數(shù)資料
型號(hào): R8J73437BGZV
廠商: Renesas Electronics America
文件頁(yè)數(shù): 23/46頁(yè)
文件大?。?/td> 0K
描述: SH-MOBILE 3AS
產(chǎn)品培訓(xùn)模塊: Electromagnetic Noise Reduction Techniques Part 1
標(biāo)準(zhǔn)包裝: 1
系列: SH-Mobile
核心處理器: SH-4A
芯體尺寸: 32-位
速度: 216MHz
連通性: I²C
外圍設(shè)備: DMA,LCD,WDT
輸入/輸出數(shù): 176
程序存儲(chǔ)器類(lèi)型: ROMless
RAM 容量: 16M x 8
電壓 - 電源 (Vcc/Vdd): 1.1 V ~ 1.3 V
封裝/外殼: 模塊
包裝: 托盤(pán)
H8
Architecture
M16C
Architecture
32-Bit RISC
Highest performance
Highest integration
32-Bit
Highest performance CISC
16-Bit
High performance,
high integration
at an aggressive price
Broadest selection of MCUs
16-Bit
Lowest cost system solution
for 8-bit applications
8-Bit
Lowest cost MCUs
H8/300L SLP series
SH-4, SH-4A series
SH-3, SH3-DSP series
SH-2, SH2-DSP, SH-2A series
H8/300H SLP series
H8/Tiny series
H8S series
H8SX series
M32C/100 series
M16C/Tiny series
R8C/Tiny series
M32C/90 series
M32C/80 series
M16C/62P series
SuperH
Architecture
Introduction
Market Needs
SuperH Solutions
Performance
Up to 1080 MIPS, 4.2 GFLOPS (SH-4A); up to 360 MIPS (SH-2A), superscalar architecture
Cost/performance
High MIPS/$ ratings
Power/performance
High MIPS/W ratings
Code efficiency
16-bit instructions: up to 40% smaller memory footprint, up to 40% more data in cache
Flash ROM
Up to 1MB flash, accessible in one cycle at 80MHz; single-voltage programmable
Floating-point and
DSP (SH2-DSP, SH3-DSP), superscalar FPU (SH-2A, SH-4, SH-4A),
DSP support
Superscalar DSP (SH-Mobile)
Graphics support
Superscalar operation [FPU operations independent of non-FPU operations] (SH-2A, SH-4, SH-4A)
2D and 3D graphics engine (SH-Mobile)
Video and Imaging
H.264, MPEG4, H.263, and JPEG engines
On-chip peripherals
Timers, DSP, MMU, A/D, D/A, memory controller, LCD controller, AFE, motor controller, cache,
BSC, crypto accelerator, more
Industry-standard
USB, Ethernet, PCI, SCI, I2C, PCMCIA, SSI (Audio), CAN, Smart Card, IrDA, SDRAM, DDR-SDRAM,
interfaces
NAND flash, memory card, camera
Architecture roadmap
Instruction set accommodates superscalar designs
Code compatibility
Upward compatible families (SH-1, SH-2, SH-3, SH-4)
Power consumption
Low static/dynamic operating currents, high MIPS/W ratings, power-down modes
Development
Comprehensive integrated H/W and S/W tools, extensive third-party support, on-chip debug
environment
Off-the-shelf solutions
Middleware, reference boards, broad OS support
Support and training
Experienced application engineers, online evaluation lab, training courses
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