I SuperH On-Chip Floating Point Co-processor Ar" />
參數(shù)資料
型號(hào): R8J73437BGZV
廠商: Renesas Electronics America
文件頁(yè)數(shù): 46/46頁(yè)
文件大?。?/td> 0K
描述: SH-MOBILE 3AS
產(chǎn)品培訓(xùn)模塊: Electromagnetic Noise Reduction Techniques Part 1
標(biāo)準(zhǔn)包裝: 1
系列: SH-Mobile
核心處理器: SH-4A
芯體尺寸: 32-位
速度: 216MHz
連通性: I²C
外圍設(shè)備: DMA,LCD,WDT
輸入/輸出數(shù): 176
程序存儲(chǔ)器類(lèi)型: ROMless
RAM 容量: 16M x 8
電壓 - 電源 (Vcc/Vdd): 1.1 V ~ 1.3 V
封裝/外殼: 模塊
包裝: 托盤(pán)
Hybrid RISC/DSP Architecture Floating Point Features
7
I SuperH On-Chip Floating
Point Co-processor
Architectural Features
Supports single-precision (32 bits)
and double-precision (64 bits)
10-stage floating instruction
pipeline (SH-4A)
Supports IEEE754-compliant
data types and exceptions
Floating-point registers:
32 bits x 16 words x 2 banks
(Single-precision x 16 words,
or double-precision x 8 words)
x 2 banks
32-bit CPU-FPU floating-point
communication register (FPUL)
Supports FMAC
(multiply-and-accumulate)
instruction
Supports FDIV (divide)
and FSQRT (square root)
instructions
Supports FLDI0/FLDI1
(load constant 0/1) instructions
3D graphics instructions
(single-precision only)
4-dimensional vector
conversion and matrix
operations (FTRV): 4 cycles
(pitch), 8 cycles (latency)
4-dimensional vector (FIPR)
inner product: 1 cycle (pitch),
5 cycles (latency)
Instruction execution times
– Latency
(FMAC/FADD/FSUB/FMUL):
3 cycles (single-precision),
8 cycles (double-precision)
– Pitch
(FMAC/FADD/FSUB/FMUL):
1 cycle (single-precision),
6 cycles (double-precision)
Versatility of the floating point co-processor
Powerful 4-way FPU for 3-D graphics
16-tap, 40-sample block FIR (1.6 MACs/cycle)
STAGE 1
STAGE 4
=x
+ ... +
y
i
y
i+1
y
i+2
y
i+3
c0
c1
c2
c3
x
i
x
i+1
x
i+2
x
i+3
x
i+1
x
i
x
i+1
x
i+2
x
i-2
x
i-1
x
i
x
i+1
x
i-3
x
i-2
x
i-1
x
i-
x
c12
c13
c14
c15
x
i-12
x
i-11
x
i-10
x
i-9
x
i-13
x
i-12
x
i-11
x
i-10
x
i-14
x
i-13
x
i-12
x
i-11
x
i-15
x
i-14
x
i-13
x
i-12
A single DIF butterfly
In1
In2
Out1
Out2
-1
W=a+jb
=
x
In1_r
In1_i
In2_r
In2_i
Out1_r
Out1_i
Out2_r
Out2_i
1
0
a
b
0
1
-b
a
1
0
-a
-b
0
1
b
-a
MULTIPLICATION
INNER PRODUCT
1024-point, radix-2 FFT (35.4 cycles)
=x
Y1
Y2
Y3
1
x1
x2
x3
1
c11
c21
c31
c41
c12
c22
c32
c42
c13
c23
c33
c43
c14
c24
c34
c44
A single SuperH
instruction, FTRV,
can perform this
matrix-vector
multiplication
every 4 cycles.
Multiplication
3-D graphics
geometry
Multiplication
3-D graphics
geometry
A single SuperH instruction, FIPR, can perform this
inner-product multiplication every cycle.
ray
d
Rn
r1
r2
r3
0
d1
d2
d3
0
x
=
I
Surface judgement
brightness
calculation
source
128-bit Floating Point Vector Engine: DSP/SIMD Instructions
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