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參數(shù)資料
| 型號(hào)： | RF2919 |
| 廠商： | RF MICRO DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 433/868/915MHZ ASK/OOK RECEIVER |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 519K |
| 代理商： | RF2919 |
11-150
RF2919
Rev A12 001113
11
T
a concern, but it can also contribute to raising the noise
floor of the receiver, thereby degrading sensitivity.
For the interface between the LNA and mixer, the cou-
pling capacitor should be as close to the RF2919 pins
as possible with the bias inductor being further away.
Once again, the value of the inductor can be changed
to compensate for trace inductance. The output imped-
ance of the LNA is on the order of several k
which
makes matching to 50
difficult. If image filtering is
desired, a high impedance filter is recommended. If no
filtering is used, the match to the mixer input need not
be a good conjugate match due to the high gain of the
IF amplifier stages. In fact, a conjugate match between
the LNA and mixer will not significantly improve sensi-
tivity, but will have an adverse effect on system IIP3
and increase the likelihood of IF instability.
Predicting and Minimizing PLL Lock Time
The RF2919 implements a conventional PLL on chip.
The VCO is followed by a prescaler, which divides
down the output frequency for comparison with the ref-
erence oscillator frequency. The output of the phase
discriminator is a sequence of pulse width modulated
current pulses in the required direction to steer the
VCO's control voltage to maintain phase lock, with a
loop filter integrating the current pulses. The lock time
of this PLL is a combination of the loop transient
response time and the slew rate set by the phase dis-
criminator output current combined with the magnitude
of the loop filter capacitance. A good approximation for
total lock time of the RF2919 is:
where D is a factor to account for the loop damping, F
C
is the loop cut frequency, C is the sum of all shunt
capacitors in the loop filter, and dV is the required step
voltage change to produce the desired frequency
change during the transient. For loops with low phase
margin (30° to 40°), use D=2 whereas for loops with
better phase margin (50° to 60°), use D=1.
To lock faster, C needs to be minimized.
1. Design the loop filter for the minimum phase margin
possible without causing loop instability problems; this
allows C to be kept at a minimum.
2. Design the loop filter for the highest loop cut fre-
quency possible without distorting low frequency mod-
ulation components; this also allows C to be kept at a
minimum.
For additional applications information, refer to the fol-
lowing technical articles.
TA0031
"Frequency Synthesis Using the RF2510"
DK1000
"ASK Transmit and Receive Chip Set"
LockTime
F
C
------
35000
C dV
+
=
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