參數(shù)資料
型號(hào): RGR2622
英文描述: Fiber Optic “Light to Logic” Receiver with Clock Recovery
中文描述: 光纖“光的邏輯”接收機(jī)時(shí)鐘恢復(fù)
文件頁數(shù): 2/6頁
文件大?。?/td> 102K
代理商: RGR2622
407
Pins 12, 14, ALARM, ALARM:
These pins provide complemen-
tary ALARM and ALARM outputs.
This is the low light alarm.
ALARM goes to a logic low
(CMOS compatible) state when
the optical power drops below
the threshold level (insufficient
optical power).
The optical power must increase
to a higher level than the level
where the alarm went low before
ALARM will return to a logic
high. This difference is the alarm
hysteresis.
Pins 17, 18, 19, 20 NC:
These pins are not connected.
Connection Diagram
Top View
Pin Descriptions
Pins 1, 2, 3, 6, 8, 13, 15, 16,
GND:
These pins should be connected
to the circuit ground.
Pins 4, 5, CLOCK, CLOCK:
These pins provide
complementary PECL CLOCK
and CLOCK outputs.
Pins 7, 9, DATA, DATA:
These pins provide complemen-
tary PECL DATA and DATA
outputs.
The RGR2622 DATA output is
noninverting, an optical pulse
causes the DATA output to go to
the PECL logic high state (+4 V
nominal).
Pin 10, PD Bias:
This pin must be connected to
any voltage from 0 V (GND) to
–5 V. This provides the photo-
diode bias. The current drawn is
directly proportional to the
average received photocurrent.
I = Responsivity x Mean Power.
The Responsivity will be between
0.8 A/W and 1.0 A/W.
Pin 11, +5 V:
This pin should be connected to
+5 V supply. The network shown
below should be placed as close
as possible to pin 11.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
GND
GND
CLOCK
CLOCK
GND
DATA
GND
DATA
PD BIAS
NC
NC
NC
NC
GND
GND
ALARM
GND
ALARM
+5 V
FIBER PIGTAIL
1 μH
+5 V
100 nF
100 nF
10 μF
PIN 11
相關(guān)PDF資料
PDF描述
RGR2622-DN Fiber Optic “Light to Logic” Receiver with Clock Recovery
RGR2622-FP Fiber Optic “Light to Logic” Receiver with Clock Recovery
RGR2622-SC Fiber Optic “Light to Logic” Receiver with Clock Recovery
RGR2622-ST Fiber Optic “Light to Logic” Receiver with Clock Recovery
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