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| 型號： | RH56D-PCI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MODEM DEVICE FAMILY FOR DESKTOP APPLICATIONS |
| 中文描述： | 調(diào)制解調(diào)器設(shè)備家庭桌面應(yīng)用程序 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 357K |
| 代理商： | RH56D-PCI |
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RH56D-PCI Modem Designer’s Guide
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Label
Pin
I/O Type
Signal Name/Description
PCI BUS INTERFACE
PCICLK
126
Ip
(in)
PCI Bus Clock.
The PCICLK (PCI Bus CLK signal) input provides timing for all
transactions on PCI. Connect to PCI Bus: CLK.
PCIRST#
124
Ip
(in)
PCI Bus Reset.
Active low input asserted to initialize PCI-specific registers,
sequencers, and signals to a consistent reset state. Connect to PCI Bus: RST#.
AD[31:0]
130-134, 136-
138, 3-6, 8-11,
23-24, 26-29,
31-32, 36-39,
41-44
I/Opts
(t/s)
Multiplexed Address and Data.
Address and Data are multiplexed on the same PCI
pins. Connect to PCI Bus: AD[31-0].
CBE0#
CBE1#
CBE2#
CBE3#
33
22
12
139
I/Opts
(t/s)
Bus Command and Bus Enable.
Bus Command and Byte Enables are multiplexed
on the same PCI pins. During the address phase of a transaction, CBE[3:0]# define
the bus command. During the data phase, CBE[3:0]# are used as Byte Enables.
Connect to PCI Bus: CBE[3:0]#.
PAR
21
I/Opts
(t/s)
Parity.
Parity is even parity across AD[31:00] and CBE[3:0]#. The master drives PAR
for address and write data phases; the Bus Interface drives PAR for read data phases.
Connect to PCI Bus: PAR.
FRAME#
13
I/Opsts
(s/t/s)
Cycle Frame.
FRAME# is driven by the current master to indicate the beginning and
duration of an access. Connect to PCI Bus: FRAME#.
IRDY#
14
I/Opsts
(s/t/s)
Initiator Ready.
IRDY# is used to indicate the initiating agent’s (bus master’s) ability
to complete the current data phase of the transaction. IRDY# is used in conjunction
with TRDY#. Connect to PCI Bus: IRDY#.
TRDY#
15
I/Opsts
(s/t/s)
Target Ready.
TRDY# is used to indicate s the Bus Interface’s ability to complete the
current data phase of the transaction. TRDY# is used in conjunction with IRDY#.
Connect to PCI Bus: TRDY#.
STOP#
17
I/Opsts
(s/t/s)
Stop.
STOP# is asserted to indicate the Bus Interface is requesting the master to stop
the current transaction. Connect to PCI Bus: STOP#.
IDSEL
144
Ip
(in)
Initialization Device.
IDSEL input is used as a chip select during configuration read
and write transactions. Connect to PCI Bus: IDSEL.
DEVSEL#
16
I/Opsts
(s/t/s)
Device Select.
When actively driven, DEVSEL# indicates the driving device has
decoded its address as the target of the current access. As an input, DEVSEL#
indicates whether any device on the bus has been selected. Connect to PCI Bus:
DEVSEL#.
REQ#
128
I/Opts
(t/s)
Reques
t. REQ# is used to indicate to the arbiter that this agent desires use of the bus.
Connect to PCI Bus: REQ#.
GNT#
127
I/Opts
(t/s)
Grant.
GNT# is used to indicate to the agent that access to the bus has been granted.
Connect to PCI Bus: GNT#.
PERR#
18
I/Opsts
(s/t/s)
Parity Error.
PERR# is used for the reporting of data parity errors. Connect to PCI
Bus: PERR#.
SERR#
19
Ood
(o/d)
System Error.
SERR# is an open drain output asserted to report address parity
errors, data parity errors on the Special Cycle command, or any other system error
where the result will be catastrophic. Connect to PCI Bus: SERR#.
INTA#
123
Ood
(o/d)
Interrupt A.
INTA# is an open drain output asserted to request an interrupt. Connect
to PCI Bus: INTA#.
PME#
85
Opod
(o/d)
Power Management Event.
Active low open drain or active high TTL output (selected
by the PME DRV bit in the EEPROM) asserted when a valid ring signal is detected at
the IRING# input and the PME_En bit of the PMCSR is a 1. This signal should be
used only if the target PCI Bus supports power management wake-up event. Connect
to the PCI Bus: PME#.
VauxDET
114
Itpd
Vaux Detect.
Active high input used to detect the presence of Vaux. Connect to PCI
Bus: Vaux. At device power on (POR), if D3_Cold bit in the EEPROM is a 1, PMC[15]
is set to a 1 if VauxDET is high or PMC[15] is cleared to a 0 if VauxDET is low.
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