參數(shù)資料
型號: RHF1201KSO2
廠商: STMICROELECTRONICS
元件分類: ADC
英文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO48
封裝: LEAD FREE, HERMETIC SEALED, SOP-48
文件頁數(shù): 10/26頁
文件大?。?/td> 328K
代理商: RHF1201KSO2
Application information
RHF1201
18/26
8.4
Clock input
The quality of the converter very much depends on the accuracy of the clock input in terms
of aperture jitter. The use of a low jitter crystal controlled oscillator is recommended.
The following points should also be considered.
The input signal must be square-shaped with sharp edges of less than 1 ns.
At 45 Msps, the duty cycle must be between 45% and 65%; in any case, the high level
clock pulse duration must be longer than 10 ns.
The clock power supplies must be independent from the ADC output supplies to avoid
digital noise modulation on the output.
When powered-on, the circuit needs several clock periods to reach its normal operating
conditions.
8.5
Power consumption optimization
The internal architecture of the RHF1201 makes it possible to optimize power consumption
according to the sampling frequency of the application. For this purpose, an external Rpol
resistor is placed between the IPOL pin and the analog ground. Therefore, the total
dissipation can be adjusted across the entire sampling range from 0.5 Msps to 50 Msps to
fulfil the requirements of applications where power saving is critical.
For low sampling frequencies, the resistor value may be adjusted to decrease the analog
current without any deterioration of dynamic performance.
The total power consumption optimization depending on the value of Rpol is as follows.
Figure 17.
Analog current consumption according to Rpol resistance
0
10203040
50
60
70
80
90
10
100
Rpol
Icca
Rpol
(k
Ω
)
-
Ic
ca
(
m
A)
Sampling Frequency, Fs (MHz)
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