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參數(shù)資料
| 型號： | RHF1201KSO2 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO48 |
| 封裝： | LEAD FREE, HERMETIC SEALED, SOP-48 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 328K |
| 代理商： | RHF1201KSO2 |
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RHF1201
Definitions of specified parameters
21/26
Effective resolution bandwidth
For a given sampling rate and clock jitter, this is the analog input frequency at which the
SINAD is reduced by 3 dB.
Pipeline delay
Delay between the initial sample of the analog input and the availability of the corresponding
digital data output on the output bus. Also called data latency. It is expressed as a number of
clock cycles.
When powered off to on, there is a delay of several clock cycles before the ADC can achieve
a reliable and stable signal conversion. During this delay, some conversion artefacts may
appear.
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