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參數(shù)資料
| 型號： | RM2211D883B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FSK Demodulator/Tone Decoder |
| 中文描述： | FSK解調(diào)器/音頻解碼器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 135K |
| 代理商： | RM2211D883B |
PRODUCT SPECIFICATION
RC2211
2
Description of Circuit Controls
Signal Input
(Pin 2)
The input signal is AC coupled to this terminal. The internal
impedance at pin 2 is 20 k
W
. Recommended input signal
level is in the range of 10 mV
RMS
to 3 V
RMS
.
Quadrature Phase Detector Output, Q
(Pin 3)
This is the high impedance output of the quadrature phase
detector, and is internally connected to the input of lock
detector voltage comparator. In tone detection applications,
pin 3 is connected to ground through a parallel combination
of R
D
and C
D
(see Figure 1) to eliminate chatter at the lock
detector outputs. If this tone detector section is not used,
pin 3 can be left open circuited.
Lock Detector Output, Q
(Pin 5)
The output at pin 5 is at a òhighó state when the PLL is out of
lock and goes to a òl(fā)owó or conducting state when the PLL is
locked. It is an open collector output and requires a pull-up
resistor, R
L
, to +V
S
for proper operation. In the òl(fā)owó state it
can sink up to 5 mA of load current.
Lock Detector Complement, Q
(Pin 6)
The output at pin 6 is the logic complement of the lock
detector output at pin 5. This output is also an open collector
type stage which can sink 5 mA of load current in the low or
òonó state.
FSK Data Output
(Pin 7)
This output is an open collector stage which requires a
pull-up resistor, R
L
, to +V
S
5 mA of load current. When decoding FSK signals the FSK
data output will switch to a òhighó or off state for low input
frequency, and will switch to a òl(fā)owó or on state for high
input frequency. If no input signal is present, the logic state
at pin 7 is indeterminate.
for proper operation. It can sink
FSK Comparator Input
(Pin 8)
This is the high impedance input to the FSK voltage
comparator. Normally, an FSK post detection or data Tlter is
connected between this terminal and the PLL phase detector
output (pin 11). This data Tlter is formed by R
Figure 1. The threshold voltage of the comparator is set by
the internal reference voltage, V
F
and C
F
of
R
, available at pin 10.
Reference Bypass
(Pin 9)
This pin can have an optional 0.1,
the ground.
m
F capacitor connected to
Reference Voltage, V
R
(Pin 10)
This pin is internally biased at the reference voltage level,
V
R
; V
R
= +V
S
/2 D 650 mV. The DC voltage level at this pin
forms an internal reference for the voltage levels at pin 3, 8,
11 and 12. Pin 10 must be bypassed to ground with a 0.1
capacitor.
m
F
Figure 1. Generalized Circuit Connection for FSK and Tone Detection
65-2211-02
0.1
μ
F
Internal
Reference
FSK
Comparator
FSK
Output
+V
S
R
L
R
B
510K
CF
R
F
100K
(12)
VCO
(14)
(13)
R0
C0
Quad
f
-Detector
(3)
CD
R
D
100K
to 470K
Input
Signal
0.1
μ
F
Input
Preamp
Loop
f
-Detector
C1
R1
Lock
Detector
Comparator
Q
Q
Lock
Detector
Outputs
(6)
(5)
(10)
(8)
(1)
(7)
(2)
(11)
f
f
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