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| 型號(hào)： | RM5271-300S |
| 英文描述： | 64-Bit Microprocessor |
| 中文描述： | 64位微處理器 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 387K |
| 代理商： | RM5271-300S |
Quantum Effect Devices
www.qedinc.com
RM5271 Microprocessor, Document Rev. 1.3
13
PIN DESCRIPTIONS
The following is a list of interface, interrupt, and miscellaneous pins available on the RM5271.
Pin Name
Type
Description
System interface:
ExtRqst*
Input
External request
Signals that the system interface is submitting an external request.
Release*
Output
Release interface
Signals that the processor is releasing the system interface to slave state
RdRdy*
Input
Read Ready
Signals that an external agent can now accept a processor read.
WrRdy*
Input
Write Ready
Signals that an external agent can now accept a processor write request.
ValidIn*
Input
Valid Input
Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid
command or data identifier on the SysCmd bus.
ValidOut*
Output
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid
command or data identifier on the SysCmd bus.
SysAD(63:0)
Input/Output
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
SysADC(7:0)
Input/Output
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data cycles.
SysCmd(8:0)
Input/Output
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an external
agent.
SysCmdP
Input/Output
Reserved for system command/data identifier bus parity
For the RM5270, unused on input and zero on output.
Clock/control interface:
SysClock
Input
System clock
Master clock input used as the system interface reference clock. All output timings are relative to
this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor
selected during boot initialization
VccP
Input
Quiet Vcc for PLL
Quiet Vcc for the internal phase locked loop. Must be connected to VccInt through a filter circuit.
VssP
Input
Quiet VSS for PLL
Quiet Vss for the internal phase locked loop. Must be connected to VssInt through a filter circuit.
Secondary cache interface:
ScCLR*
Output
Secondary Cache Block Clear
Requests that all valid bits be cleared in the Tag RAMs. Many RAM’s may not support a block clear
therefore the block clear capability is not required for the cache to operate.
ScCWE*(1:0)
Output
Secondary Cache Write Enable
Asserted to cause a write to the cache. Two identical signals are provided to balance the capacitive
load relative to the remaining cache interface signals.
ScDCE*(1:0)
Output
Secondary Cache Data RAM Chip Enable
When asserted this signal causes the data RAM’s to read out their contents. Two identical signals
are provided to balance the capacitive load relative to the remaining cache interface signals
ScDOE*
Input
Secondary Cache Data RAM Output enable
When asserted this signal causes the data RAM’s to drive data onto their I/O pins. This signal is
monitored by the processor to determine when to drive the data RAM write enable in a secondary
cache miss refill sequence.
ScLine(15:0)
Output
Secondary Cache Line Index
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