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參數(shù)資料
| 型號： | RM5271-300S |
| 英文描述： | 64-Bit Microprocessor |
| 中文描述： | 64位微處理器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大小： | 387K |
| 代理商： | RM5271-300S |
18
RM5271 Microprocessor, Document Rev. 1.3
Quantum Effect Devices
www.qedinc.com
System Interface Parameters
1
Boot-Time Interface Parameters
Parameter
Symbol
Test Conditions
I/O Bus Speed
Units
200 MHz
Min
250–350 MHz
Min
Max
Max
Data Output
2,3
t
DO
mode14..13 = 10
5
(fastest)
1.0
4.5
1.0
4.0
ns
mode14..13 = 11
5
1.0
5.0
1.0
4.0
ns
mode14..13 = 00
5
1.0
5.5
1.0
4.0
ns
mode14..13 = 01
5
(slowest)
1.0
6.0
1.0
4.5
ns
Data Setup
4
t
DS
t
rise
= see above table
t
fall
= see above table
2.5
2.5
ns
Data Hold
4
t
DH
1.0
1.0
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Timings are measured from 1.5V of the clock to 1.5V of the signal.
Capacitive load for all output timings is 50pF.
Data Output timing applies to all signal pins whether tristate I/O or output only.
Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
Only mode 14..13 = 10 (fastest) is tested and guaranteed.
Parameter
Mode Data Setup
Symbol
t
DS
(M)
Test Conditions
I/O Bus Speed
50/67/75/83/87/100/125 MHz
Units
Min
4
Max
SysClock cycles
Mode Data Hold
t
DH
(M)
0
SysClock cycles
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