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參數(shù)資料
| 型號(hào)： | RM7000-200T |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | 64-BIT, 200 MHz, RISC PROCESSOR, PBGA304 |
| 封裝： | 31 X 31 MM, TBGA-304 |
| 文件頁(yè)數(shù)： | 38/54頁(yè) |
| 文件大?。?/td> | 901K |
| 代理商： | RM7000-200T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
38
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 16 Boot Time Mode Stream
Mode bit
Description
Mode bit
Description
0
reserved (must be zero)
17..16
System configuration identifiers - software visible
in processor Config[21..20] register
4..1
Write-back data rate
0:
1:
2:
3:
4:
5:
6:
7:
8:
9-15: reserved
DDDD
DDxDDx
DDxxDDxx
DxDxDxDx
DDxxxDDxxx
DDxxxxDDxxxx
DxxDxxDxxDxx
DDxxxxxxDDxxxxxx
DxxxDxxxDxxxDxxx
19..18
Reserved: Must be zero
7..5
SysClock to Pclock Multiplier
Mode bit 20 = 0 / Mode bit 20 = 1
0:
1:
2:
3:
4:
5:
6:
7:
Multiply by 2/x
Multiply by 3/x
Multiply by 4/x
Multiply by 5/2.5
Multiply by 6/x
Multiply by 7/3.5
Multiply by 8/x
Multiply by 9/4.5
20
Pclock to SysClock multipliers.
0:
1:
Integer multipliers (2,3,4,5,6,7,8,9)
Half integer multipliers (2.5,3.5,4.5)
8
Specifies byte ordering. Logically ORed with
BigEndian input signal.
0:
1:
Little endian
Big endian
23..21
Reserved: Must be zero
10..9
Non-Block Write Control
00:
01:
10:
11:
R4000 compatible non-block writes
reserved
pipelined non-block writes
non-block write re-issue
24
JTLB Size.
0: 48 dual-entry
1: 64 dual-entry
11
Timer Interrupt Enable/Disable
0:
1:
Enable the timer interrupt on IP[5]
Disable the timer interrupt on IP[5]
25
On-chip secondary cache control.
0:
1:
Disable
Enable
12
Enable the external tertiary cache
0:
1:
Disable
Enable
26
Enable two outstanding reads with out-of-order
return
0:
1:
Disable
Enable
14..13
Output driver strength - 100% = fastest
00:
01:
10:
11:
67% strength
50% strength
100% strength
83% strength
255..27
Reserved: Must be zero
15
External Tertiary cache RAM type:
0:
1:
Dual-cycle deselect (DCD)
Single-cycle deselect (SCD)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM7000-225S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-250S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM7000-250S | 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000263S | 制造商:QED 功能描述:* |
| RM7000-263S | 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA 制造商:Quantum Effect Design 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000-266T | 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000-300T | 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
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