- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376314 > RM7000-263S (PMC-Sierra, Inc.) RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released PDF資料下載
參數(shù)資料
| 型號(hào)： | RM7000-263S |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| 中文描述： | RM7000⑩微處理器與片上二級(jí)高速緩存數(shù)據(jù)發(fā)布 |
| 文件頁數(shù)： | 34/54頁 |
| 文件大小： | 901K |
| 代理商： | RM7000-263S |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002175, Issue 1
34
RM7000
Microprocessor with On-Chip Secondary Cache Datasheet
Released
Table 10 Performance Counter Control
PerfControl
Field
Description
The performance counter interrupt will only occur when interrupts are enabled in the
Status
register, IE=1, and
Interrupt Mask
bit 13 (
IM[13]
) of the coprocessor 0 interrupt control register is
not set.
4..0
Event Type
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
0A:
0B:
0C:
0D:
0E:
0F:
10:
11:
12:
13:
14:
15:
Clock cycles
Total instructions issued
Floating-point instructions issued
Integer instructions issued
Load instructions issued
Store instructions issued
Dual issued pairs
Branch prefetches
External Cache Misses
Stall cycles
Secondary cache misses
Instruction cache misses
Data cache misses
Data TLB misses
Instruction TLB misses
Joint TLB instruction misses
Joint TLB data misses
Branches taken
Branches issued
Secondary cache writebacks
Primary cache writebacks
Dcache miss stall cycles (cycles where both cache miss tokens taken and a third
address is requested)
Cache misses
FP possible exception cycles
Slip Cycles due to multiplier busy
Coprocessor 0 slip cycles
Slip cycles doe to pending non-blocking loads
Write buffer full stall cycles
Cache instruction stall cycles
Multiplier stall cycles
Stall cycles due to pending non-blocking loads - stall start of exception
16:
17:
18:
19:
1A:
1B:
1C:
1D:
1E:
7..5
Reserved (must be zero)
8
Count in Kernel Mode
0:
1:
Disable
Enable
9
Count in User Mode
0:
1:
Disable
Enable
10
Count Enable
0:
1:
Disable
Enable
31..11
Reserved (must be zero)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM7000-266T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-300S | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7000-300T | RM7000⑩ Microprocessor with On-Chip Secondary Cache Datasheet Released |
| RM7935 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
| RM7965 | 64-bit Microprocessors with Integrated L2 Cache and EJTAG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM7000-266T | 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000-300T | 制造商:QED 功能描述: 制造商:QED 功能描述:Microprocessor, 64 Bit, 304 Pin, Plastic, BGA |
| RM7000A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with Integrated L2 Cache |
| RM7000A-300T | 制造商:Quantum Effect Devices 功能描述:64-BIT, 300 MHz, MICROPROCESSOR, 304 Pin Plastic BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。