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| 型號： | RM7065A-300T |
| 廠商： | PMC-Sierra, Inc. |
| 英文描述： | RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary |
| 中文描述： | RM7065A⑩微處理器與片上二級高速緩存的數(shù)據(jù)資料的初步 |
| 文件頁數(shù)： | 13/52頁 |
| 文件大小： | 776K |
| 代理商： | RM7065A-300T |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
13
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Figure 2 is a simplification of the pipeline section and illustrates the basics of the instruction issue
mechanism.
Figure 3 Instruction Issue Paradigm
The figure illustrates that one F pipe instruction and one M pipe instruction can be issued
concurrently but that two M pipe or two F pipe instructions cannot be issued. Table 2 specifies
more completely the instructions within each class.
Table 2 Dual Issue Instruction Classes
4.3
Pipeline
The logical length of both the F and M pipelines is five stages with state committing in the register
write, or W, pipe stage. The physical length of the floating-point execution pipeline is actually
seven stages but this is completely transparent to the user.
Figure 4 shows instruction execution within the RM7065A when instructions are issuing
simultaneously down both pipelines. As illustrated in the figure, up to ten instructions can be
executing simultaneously. This figure presents a somewhat simplistic view of the processors
operation since the out-of-order completion of loads, stores, and long latency floating-point
operations can result in there being even more instructions in process than what is shown.
integer
add, sub, or,
xor, shift, etc.
load/store
lw, sw, ld, sd,
ldc1, sdc1,
mov, movc,
fmov, etc.
floating-
point
fadd, fsub,
fmult, fmadd,
fdiv, fcmp,
fsqrt, etc.
branch
beq, bne,
bCzT, bCzF, j,
etc.
F Pipe
Integer
M Pipe
Integer
F Pipe
FP
M Pipe
FP
Cache
Instruction
Unit
Dispatch
F Pipe IBus
M Pipe IBus
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